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codeofvhdl2006
- 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
0
- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
8bit_adder_AND_4x4_Multiplier
- 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog descr iption! ! !
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
bit4_mul
- vhdl写的程序，并行4位乘法器 加快流据传递，提高算法效率-bit4_mul
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog
4X
- VHDL实现的4位乘法器，绝对好用，libero8.5仿真没问题！-VHDL implementation of the 4-bit multiplier
Sainty2
- 里边有一个半加器。、一个全加器、一个触发器和一个无符号4乘4的乘法器程序，可以完成4位无符号数相乘-Inside there is a half adder. , A full adder, a flip-flop, and an unsigned 4 by 4 multiplier process can be completed by multiplying the number of 4-bit unsigned
vhdl
- 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) end one_bit_adder -4-bit multipl
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
verilog5
- 用verilog语言编写的4位乘法器程序。通过循环移位进行4位二进制数的乘法运算。压缩包内也包含此4位乘法器程序的modelsim仿真文件。-Verilog language with 4-bit multiplier process. By cyclic shift for 4-bit binary number multiplication. This compressed package also contains four multipliers modelsim simulation
mult_16
- 这是自己设计的16位乘法器设计，其中用了booth编码，，4-2压缩器等，-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
16-bit-parallel-mult
- 16位并行乘法器， 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
VHDL_book2
- add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
MUL
- 4位乘法器用来监测心跳到，与计数器搭配使用-this is 4 multiply to get heart beats
e55_mul_addtree
- 实现4位乘法器的流水线操作计算，便于理解流水线(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining)
FIR
- 采用加法树设计8位乘法器，具有流水线结构7阶FIR滤波器，输入序列信号字长4位表示，并且是无符号数。(An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.)