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1下载：
ALTERA sdram
vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
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ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。
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Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
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标准SRD SDRAM控制器参考设计，altera提供
Verilog代码,带有使用手册，大家试试交流一下
-Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
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Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
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Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
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SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
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此為採用ALTERA所做的DDR 控制器(verilog)-
File/Directory Descr iption
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\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route
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ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
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基于Verilog HDL的SDRAM控制器。
实验条件：
工具：Quartus II 6.0 ,SignalTap II
FPGA：Altera Cyclone EP1C12Q240C8N
SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclon
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altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
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SDRAM_96M_串口实验OK 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-SDRAM_96M_ serial experiments OK a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
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DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
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This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
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使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
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此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
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sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
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