搜索资源列表
UDPCOMDISP7-25
- 下位机是ARM2440，基于winCE6.0，程序接受上位机的网络图像数据在界面上适时显示，通信协议基于UDP，是一个嵌入式视频监控程序，基于VS2005，C++开发，源码对图像视频接受显示做了深入研究，在本项目中调试运行通过，也是业内仅有的公开源码-Lower machine is ARM2440, based winCE6.0, PC network program accepts image data in the interface time display, communication
eddy-current
- 设计一种快速涡流探伤仪 能够对有裂纹的金属表面 进行探伤 ，根据不同深度，不同大小裂纹，进行相应报警，检测灵敏度高。采用c语言编程，运行环境为keil -Eddy current flaw detector can quickly design a cracked metal surface of the flaw detection, depending on the depth of the crack of different sizes for the corresponding ala
bomb
- In-depth understanding of the computer system C language code that describes the algorithm for the realization and understanding of the bomb
verilogHDL
- verilogHDL 精粹讲解，还有很多经典实例，有助于大家更深入地学习verilogHDL。-verilogHDL explain the essence, there are many classic examples to help you more in-depth study verilogHDL.
float-erjinzhi
- 浮点数的二进制学习笔记 有利于深入理解浮点数-The study notes floating point binary floating-point number in favor of in-depth understanding
ONVIFExample
- onvif的实现实例，帮助你直观认识onvif的实现流程调用方法，里面是实现的完全代码，比较复杂，适合深入学习者-implementation examples onvif help you achieve an intuitive understanding of the process calling the method onvif, which is completely code, more complex, for in-depth learner
rtc
- NIOS II下进行RTC实时时钟的开发,比较有难度的知识点： 1. PIO的深度应用； 2. C语言中函数指针的应用； 3. DS1302的驱动编写； 4. C语言中程序的模块化书写方式； -NIOS II development for the next RTC real time clock, have more knowledge of difficulty: . 1 PIO depth application 2 Application
Handout
- 创建图的邻接表存储结构,输出邻接表数据(验证创建过程),深度优先遍历(DFS) ,广度优先遍历(BFS),增加一个顶点到图, 删除一个顶点(同时删除其所有邻接边) ,增加一条弧到图,从图中删除一条弧- Creating adjacency table storage structure, the output adjacency table data (validation creation process), depth-first traversal (DFS), breadth-fi
FPGA-teach1
- 这是一种Verilog语言的学习资料的第一部分，能够很深入的帮助学习进步-This is the first part of a Verilog language learning materials, and can be very in-depth help learning progress
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
FSMC
- STM32 彩屏程序 此程序有一点的深度 对提高STM32很有帮助-STM32 procedures this program a little color depth to improve the STM32 helpful
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
ballclock
- 数据结构小应用，球钟。用来加深对数据结构的理解，深入学习很有帮助-Small application data structures, ball bell. To deepen the understanding of data structures, in-depth study helpful
ARMv7M
- 这是一篇讲ARMV7体系结构的文章英文的。通过它可以让读者深入的了解CORTEX-M4体系结构。-This is an article talking about ARMV7 English architecture. It allows the reader through in-depth understanding CORTEX-M4 architecture.
c51100
- 单片机100实例程序,可以通过此文档更深入的学习和了解单片机原理。-SCM 100 sample program, this document can be more in-depth study and understanding of SCM principles.
main
- 超声波测水深C++源代码，可在Keil4运行，已调试。-Ultrasonic measuring depth C++ source code can be run in Keil4, debugging.
flow-field-inside-the-car
- 立空调系统与车厢内部空间的整体模型,对整体流场进行数值模拟。全面深入的 研究列车高速运行、进出隧道和会车时,车内的气流组织情况和空气质量的好坏 是极为必要的。 -Location, air distribution mode, the selection of fan parameters and to the air conditioning system of the train, so must be built Set the air conditioning syste
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
zedboard_CTT_v2013_2_130807
- 在文档里包含有Xilinx公司的软件Vivado的实验教程，可以尽快的对zedboard有个深入的学习了解，有助于初学者的快速学习-In a document containing the Xilinx Vivado experimental tutorial software, you can as soon as possible to have a depth of zedboard learn about, to help beginners learn fast