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unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164
motor_control
- LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL
hdb3
- hdb3编码源程序完整版，内含插B，插V程序，功能完整，欢迎下载-library ieee use ieee.std_logic_1164.all entity hdb3 is port(codein: in std_logic clk : in std_logic clr : in std_logic --复位信号 codeout: out std_logic_vector
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
VHDLSaler
- 文件名：pl_auto1.vhd。 --功能：货物信息存储，进程控制，硬币处理，余额计算，显示等功能。 --说明：显示的钱数coin的 以5角为单位。-library ieee use ieee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic
vhdl
- 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) end one_bit_adder -4-bit multipl
12
- 4位除法器 library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port ( DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LO
1
- 一个VHDL实现的测频计 LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY freq IS PORT( Fsignal : IN std_logic -- Rst : IN std_logic Gate : IN std_logic Ready : OUT std_lo
2
- 使用变量的状态机 library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT(clock,x : IN BIT z : OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0,s1,
library-ieee
- 通过逐列扫描来显示汉字。 现实的为“08电气2”的字样。 拓展功能为向左滚动 由开关控制滚动 红字为字库部分，控制所要显示的是什么汉字 蓝字为分频模块，控制扫描频率与滚动速度 绿字为逐列扫描模块，-By-column scan to display Chinese characters. The reality of the "08 Electric 2" message. Scroll left to expand functions, controlled by a
library-ieee
- Look up table in vhdl
LIBRARY-IEEE
- 底层文件2：h_subber.VHD实现一位半减器 顶层文件：f_subber.VHD实现一位全减器 -The underlying file 2: h_subber.VHD-to achieve a half- Top-level file: f_subber.VHD the realization of a full subtracter
sy5
- 移位寄存器 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) --来自0809转换好的8位数据 CLK : IN STD_LOGIC --状态机工作时钟 EOC : IN STD_LOGIC --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC --8个模拟信号通道地址锁存信号 START
LIBRARY-IEEE
- 8位数码管的动态显示（包括对数码管的位选以及段选）-8 digital control dynamic display
fpq
- 分频器源码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY fpq IS PORT(clk:IN STD_LOGIC clk_out:OUT STD_LOGIC) END fpq ARCHITECTURE hh OF fpq IS CONSTANT m : INTEGER:= 5 SIGNAL tmp:STD_LOGIC BEGIN PROCESS(clk,tmp) V
library-ieee
- 用VHDL语言编写的锯齿波，并且包括锁存器的生成代码-With the VHDL language sawtooth, and latch generate code
LIBRARY-IEEE
- 将1Mhz的频率信号转换成29hz的频率。分频器-Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider
vhdl416yima.doc
- 四十六译码器 是用if语句描述的-library IEEE use IEEE.std_logic_1164.all entity encoder4_16 is port ( d: in STD_LOGIC_VECTOR (3downto0) q: out STD_LOGIC_VECTOR (15downto0)) end encoder4_16 architecture encoder_if of encoder4_16 is begin
practica1
- tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk :
Filterfgfftd
- LIBRARY ieee USE ieee.std_logic_1164.ALL library work use work.fft_pkg.all