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Floating point library for the 8052
- 8052单片机的浮点数运算库汇编语言源代码，可用于单片机的浮点数运算使用。Floating point library for the 8052.
Fast Floating-Point Arithmetic Emulation on the Bl
- ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
12864_draw.LCD12864画点，画直线，画圆和画图片算法
- LCD12864画点，画直线，画圆和画图片算法，包括程序和图片,LCD12864 painting point, drawing a straight line, and painting pictures drawcircle algorithm, including the procedures and picture
libwma.rar
- 在mplayer播放器增加wma的定点运算补丁，44100的采样率文件播放没有问题，22050采样率文件播放有噪音。,Mplayer player in the fixed-point increase in computing patch wma, 44100 sampling rate of file to play no problem, the sampling rate of 22,050 documents have noise playback.
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
32-float-point-adder
- 32位浮点加法器。我第一次上载源码你就放过我吧，我就是想看一看加法器应该怎么做。-Floating point adder
float_mul_verilog
- 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
fudianshuyunsuan
- 介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
touch-tslib
- 几个触摸屏笔点校验算法讲解，还有系统自带触摸屏校验算法。包括三点校验和五点校验。-Several touch-screen pen-point calibration algorithm is explained, as well as Linux comes with touch-screen calibration algorithm. Including three five-point calibration and verification.
lpc
- 用AD的16位定点DSP作音频压缩器-With AD 16-bit fixed-point DSP for audio compressor
floating-point-adder1
- 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
Primal-Dual-Interior-Point-Methods--StephenJ.Wrigh
- Primal-Dual Interior-Point Methods - Stephen J.Wright.pdf不知是否有人需要,讲有约束优化的好书.-Primal-Dual Interior-Point Methods- Stephen J.Wright.pdf 1997 Written by Stephen J.Wright.
floating-point-adder
- verilog implementation of the floating point adder
floating-point-multiplier
- verilog implementation of the floating point multiplier
[Source code] 1024 point DFT n FFT
- 1024 point DFT & FFT (radix2 decimation in frequency)