搜索资源列表
multiply
- 四位加法器的VHDL代码，实现四位加法器FPGA实现。-Four adder VHDL code to achieve the four adder FPGA.
exp1
- 加法器，基于FPGA二进制的加法器，vhdl语言-Adder, FPGA-based binary adder, vhdl language
adder4_1
- 基于VHDL的四位加法器，运行环境quartus-VHDL-based four adder, operating environment quartusII
Adder-digital-display
- 基于FPGA的用VHDL程序编写的加法器数码显示程序-FPGA-based programming with VHDL adder digital display program
exp1.7_adder
- 用VHDL及verylog语言设计一个加法器，可以在Quartus II中仿真-Language Design with VHDL and verylog an adder, in the Quartus II simulation
BCD-adder
- 用VHDL语言设计一个BCD码加法器，输入A[3..0]、B[3..0],输出为SUM[4..0]。-bcd adder
eightbitadd
- 用VHDL语言实现8位的并行加法器，不同于行波进位加法器-8-bit parallel adder with VHDL, unlike the ripple carry adder
EDA_examples
- 此为四比特加法器，对于VHDL的初学者来说具有较大用途，运用的是ISE的开发软件，仿真结果正确。-This is four Bite Jia instruments used in, for the larger purpose of VHDL beginners, the use of the ISE development software, simulation results are correct.
1_ADDER
- ＣＰＵ内部的加法器用ｖｈｄｌ语言在可编程逻辑器件上的实现-Within the CPU is VHDL language addition in programmable logic devices for fulfillment
100vhdl
- VHDL语言100例，第1例 带控制端口的加法器，第2例 无控制端口的加法器等-VHDL language 100 cases, 1 case with a control port adder, two cases of the control port adder and so on. . .
jiafa
- 基于QUTER的VHDL言语的加法器设计-Based on the words of the QUTER VHDL adder design
Eight-parallel-adder
- 8 位并行加法器 vhdl 语言描述-Eight parallel adder
Desktop
- 四D触发器，最优先级编码器和加法器描述的VHDl文件-Four D flip-flop, the priority encoder and adder descr iption of the VHDl files
five
- 并入串出寄存器完成双向含异步清0和同步时钟使能的4位加法器的VHDL描述，并对其进行波形仿真，确定结果正确。- Incorporated into the string to the register to complete the two-way with asynchronous clear and synchronous clock so that the VHDL descr iption of the four adder energy and waveform simulatio
acc8
- VHDL语言设计八位加法器，可用于CPU中的加法模块，-VHDL language eight adder, adder module can be used for the CPU,
adder
- 基于FPGA的加法器的设计，QuartusII编译通过，采用VHDL语言编写。-The adder on FPGA design, QuartusII compile, USES the VHDL language.
fudian_sub
- 实现32位浮点减法器，具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
fudian_mul
- 实现32位浮点减法器，具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
jiafaqi
- 利用FPGA，VHDL设计一个加法器控制LED。-The use of FPGA, VHDL design an adder control LED.
adder_s
- 八位并行加法器，同时进位，利用VHDL语言，在ISE环境中建立工程-Eight parallel adder