搜索资源列表
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Music_LiangZhu
- FPGA音乐试验,语言:verilog HDL-A FPGA expperientation which can play music Liangzhu,language:verilog HDL
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
veriloghdl_teaching_model
- Verilog HDL权威教程,建模实例及语法参考和其他论题- Authority Verilog HDL tutorials , modeling examples and reference grammar ,other topics.
CCD_DRIVER
- verilog HDL语言,线性CCD1501D驱动程序,基于FPGA,其他线性传感器可参照修改。-verilog HDL language, linear CCD1501D driver, based on the FPGA, the other linear sensor can be modified by reference.
VerilogHDL_code
- 几个常用的接口实验的程序代码,用Verilog HDL语言编写的,包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees
SPI_verilog_mycode
- 基于Verilog HDL的SPI代码,可在FPGA上实现SPI接口,请大家参考-Verilog HDL based on the SPI code, implementation in FPGA on SPI interface, please refer to
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA,适合于FPGA及Verilog HDL的初学者,配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
veriloghdlcsdm
- 用verilog hdl 硬件描述语言写的一个范例程序,led的,扩展性极强,欢迎大家下载使用。-Verilog hdl using hardware descr iption language to write an example of the procedure, led, and highly scalable, welcome to download.
fifo8
- FIFO 源程序,verilog HDL实现,自己验证过,没问题-FIFO source, verilog HDL to achieve their own verified, no problem
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
TRL_Design_of_a_asynchronous_bit_serial_data_trans
- RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据,执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behavi
shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写,其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路,在J钟信号到来时状态产生变化, CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态,具有数据装入、数据保持、循环右移、带进位循环右移,循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入,通过键5 产生高低电平M 控制工作模式, M=l 时带进位循环移位,由键8 控制CO 为允许带进位移位输入,由键7 控制:S 控制移位模式0-3 ,由键6 控制
uart
- uart using verilog hdl
veriloghdl
- 多路选择器(MUX)verilog hdl 多路选择器(MUX)verilog hdl-MUX (MUX) verilog hdl multiplexer (MUX) verilog hdl
MAC_rd
- DM9000A读寄存器模块, verilog HDL-read DM9000A registers , in verilog HDL
Ps2-ALL
- PS2键盘鼠标接口控制实现电子琴功能,verilog hdl 编写-PS2 keyboard and mouse interface to control the realization of organ function, verilog hdl prepared
uart_txd
- 基于verilog hdl的UART串口发送子程序。-Verilog hdl a UART-based serial port to send subroutine.
20081129464173846
- 介绍Verilog HDL, 内容包括: – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in