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一些VHDL源代码
- 内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
bulksrc
- 毕业课题部分程序: CY7C68013 Bulk IN 68013工作在AUTO IN模式,16位总线 SLAVE FIFO.MASTER是 ADI BF533。
16×4bitFIFO
- 16×4bit的FIFO设计,VHDL语言编的的,能在ISE上仿真出来结果。
同步FIFO设计
- 用16*8 RAM实现一个同步先进先出(FIFO)队列设计。由写使能端控制该数据流的写入FIFO,并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
trunk-hdlc.rar
- 高级链路层协议的实现,vhdl,fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
FIFO_2
- VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
1bitled
- SSI对从外设器件接收到的数据执行串行到并行转换。CPU可以访问SSI数据寄存器来发送和获得数据。发送和接收路径利用内部FIFO存储单元进行缓冲,以允许最多8个16位的值在发送和接收模式中独立地存储。 使用 ssi 控制1位数码管的显示-SSI received from peripheral devices to the implementation of the serial to parallel data conversion. CPU can access data regi
VHDL06
- 16×4bit的FIFO设计代码,学习代码,请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
THS1206
- FPGA来实现数据采集,AD采用TI公司的THS1206,高速并行AD,内含16字FIFO,降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
XR16M2550
- XR16M2550是一款高性能,具有16字节收发FIFO的异步全双工UART芯片,具有两路完全独立的UART通道。本资料包含完整的测试代码(ADS 1.2环境),中文应用文档,电路原理图,PPT讲解稿等。-XR16M2550 is a high-performance, with 16-byte receive FIFO, asynchronous full-duplex UART chip, with two-way completely independent UART channels.
SC28L198
- SC28L198是一个带有8个全双工异步通道UART的芯片,每个UART通道的接收器和发送器都拥有16字节深度的FIFO。芯片的每个UART通道除了基本的异步通信功能外,还可实现软件流控制(in-band flow control)、硬件流控制(out-of-band flow control)、以及多点模式(唤醒模式或RS-485模式)等,同时每个UART都有4个外扩的I/O引脚,每个外扩I/O引脚都为功能复用。 本资料包含完整测试程序,应用文档,电路原理图及PPT演示文档等。-SC28L
versatile_fifo_latest.tar
- 用16*8 RAM实现一个同步先进先出(FIFO)队列设计。由写使能端控制该数据流的写入FIFO,并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。-versatile_fifo
verilogfile
- 设计一个同步FIFO,该FIFO 深度为16,每个存储单元的宽度为8 位,要求产生FIFO 为 空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-16*8bit fifo
libftdi-0.16.tar
- libftdi - A library (using libusb) to talk to FTDI s UART/FIFO chips including the popular bitbang mode. Main developers: Intra2net AG <opensource@intra2net.com>-libftdi - A library (using libusb) to talk to FTDI s UART/FIFO chips i
FIFO
- verilog 实现FIFO存储功能,八位数据宽度,16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
fifo
- 一个同步FIFO,该FIFO深度为16,每个存储单元的宽度为8位,产生FIFO为空、满、半满、溢出标志。-A synchronous FIFO, the FIFO depth of 16, each storage unit width of 8, asked to produce the FIFO is empty, full, half full, the overflow flag.
STC15F-FIFO
- STC15F2K60S2实现串口FIFO,MODBUS RTU协议,支持03 16指令8继电器,8ADC,8IO采集-STC15F2K60S2 achieve serial FIFO, MODBUS RTU protocol to support 0316 instruction 8 relay, 8ADC, 8IO collection
Ex004-FIFO_V2.0_2011-10-16
- KEY Scan FIFO for STM32F103
Synchronous FIFO
- 用16*8 RAM实现一个同步先进先出(FIFO)队列设计。由写使能端控制该数据流的写入FIFO,并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writi