搜索资源列表
jibengongtestbench
- testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
RAM
- 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
doublefloat_RAM
- 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
dual ram
- 此文件是FPGA工程文件，包含了dualram的设计代码和testbench代码，使用了verilog hdl编写，仿真结果符合设计要求。
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
32_by_8_RAM
- 32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
syncram
- verilog rtl and testbench code for single port sync ram
RS422_UART
- RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
inout
- 用于RAM的测试文件，以及testbench-some RAM testingfiles，and its testbench