搜索资源列表
VHDL
- 介绍Verilog HDL, 内容包括:Verilog应用,Verilog语言的构成元素,结构级描述及仿真 ,行为级描述及仿真,延时的特点及说明 介绍Verilog testbench,激励和控制和描述 结果的产生及验证,任务task及函数function 用户定义的基本单元(primitive),可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language
testbench
- 视频转换测试程序,实现在芯片上进行视频加载-Video conversion test program
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
UART_rx_tx
- 串口单字节自发自收程序,内含testbench-UART single-byte receive and send program in includes testbench
uart2bus_latest.tar
- 文档详尽、已验证的UART工程,含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
guidencetowriteefficienttestbenchfile
- guidence to write efficient testbench file.pdf 非常非常好-guidence to write efficient testbench file.pdf very, very good
8051vlog
- 8051IP核,verilog源代码,包含测试向量,-8051 IP Core verilog code, with testbench
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
FIR
- 14阶FIR滤波器的硬件实现,附加testbench与Matlab验证.-a FIR with 14 taps, packed with testbench and matlab verification
UART
- UART发送verilog源码,波特率115200,以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
VHDL
- 分别采用行为描述,数据流描述和结构描述 编写的VHDL代码 同时,含有各自的testbench-Behavioral descr iptions were used, the data flow schema descr iption and VHDL code written at the same time, with their testbench
Decoder_3_to_8
- Testbench to generate some stimulus and display the results for the 3-to-8 decoder module
model_adder
- 包括一个基于Quartusii的加法器工程,以及基于ModelSim的前仿真、综合后功能仿真和布局布线后时序仿真的完整例程及testbench文件,吐血推荐,非常有用!-Includes an adder based Quartusii works, and the first based on ModelSim simulation, synthesis functional simulation and post layout timing simulation after complete
test-bech-of-adder8
- this is a testbench of 8 bit adder
small-programs-using-verilog
- 148个用verilog编写的小程序,易于初学者学习,部分代码还有testbench-148 small programs written using verilog, easy for beginners to learn, there are some code testbench
VHDLTESTBENCH
- 本文档对编写vhdl的testbench具有很大的参考价值,偶那个多方面考虑的-The preparation of this document, the testbench vhdl of great reference value, even considering that many
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型,包括以下4个部分:RTL源代码,测试平台,软件仿真代码,说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包,它包括以下4部分:RTL源代码,测试平台,软件仿真文件,说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
testbench
- 介绍如何编写verilog的仿真程序,很适合初学者-How to write verilog simulation program, it is suitable for beginners