搜索资源列表
Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
SDCard_Controller.rar
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 ,SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
pci.tar.gz 完成WB BUS和PCI bus之间的传输
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transact
wbspec_b4
- wishbone总线的规范介绍，很详细，很不错-wishbone bus specification describes, in great detail, very good
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
spi_wishbone
- spi wishbone bus code
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
wb_lcd
- 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
wb_to_amba_latest.tar
- wishbone总线到AMBA总线的转换，做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
uart_wb
- 兼容wishbone bus的uart模块，方便用户修改，时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when
spilicheng
- spi接口的wishbone总线的实现，能够实现spi控制器的基本功能，书上例程-spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine
wishbone-flash-
- wishbone总线的Flash闪存接口设计的相关资料-relevant information wishbone bus Flash memory interface design