搜索资源列表
Add64
- arm 上的64位加法，将32位加法扩展到64位，同理很容易扩大到128位-arm of the 64 Adder, 32 Adder expanded to 64, empathy can be easily expanded to 128
SWI
- ADS环境下软中断实现64位整数加法 运行于arm920T-ADS environment to achieve soft-interrupt 64-bit integer adder running on the ARM920T
mipssingelcycle
- mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding
Prefix_KoggeStone_32
- 经典的kogge-stone加法器结构，32结构，verilog代码-Classic kogge-stone adder structure, 32 structure, verilog code
2-51LED362
- 51单片机开发板二进制加法试验，p2口八个灯作二进制加法-51 binary adder test chip development board, p2 port lights for eight binary adder
vhdl
- vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的-vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on
32bit_pipeline_adder
- 基于HSPICE的32位流水线加法器设计-HSPICE-based 32-bit pipelined adder design
FPGA
- 简单的三人表决、一位全加器、三八译码器的VHDL语言的实现-Three simple voting, a full adder, the three eight decoder ，use VHDL language
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
add_verilog
- 2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过-Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output