搜索资源列表
8051core-Verilog
- VERILOG编写的80C51单片机内核程序
Verilog(clock)
- 用VERILOG语言编写的电子钟程序.是用GW48教学实验箱仿真
Verilog
- DDS，FPGA产生，用verilog语言实现
Verilog+130
- verilog例子，有130多个，值得参考，新手很有帮助
LCD.LCD显示的完整代码
- LCD显示的完整代码，采用Verilog编写！！！！！！！！,LCD display complete code, the use of Verilog to prepare
ledcount60.verilog语言书写 用数码管显示
- verilog语言书写 用数码管显示，60位的计数器，加上分频模块可以实现时钟功能,verilog language digital display, 60-bit counter, together with the sub-frequency clock function modules can be achieved
mcu-cpld-spi.mcu与cpld之间spi接口程序
- mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块,mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
用EPM1270实现的1602液晶驱动Verilog
- 用EPM1270实现的1602液晶驱动Verilog,EPM1270 achieved by 1602 LCD driver Verilog
Source.rar
- PWM Verilog源代码，可以通过仿真测试,PWM Verilog source code, can be tested through simulation
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
TFTDriverNew_V2
- TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
AD9910
- 这是AD9910 DDS芯片的verilog配置程序，经调试已成功，可以供大家参考。-AD9910 verilog configuation.
Verilog
- Verilog经典参考书籍，为周立功公司为了方便国内读者学习Verilog而写的一本详尽的参考书。-Classic Verilog reference books for the week of meritorious service for the convenience of domestic companies to learn Verilog reader written a detailed reference book.
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
rom
- Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
USB_kz
- 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
seg7led
- Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through
RS485
- 用VERILOG语言写的RS485通信程序,经调试可以直接使用-Verilog language used to write the RS485 communication program, the debugger can be used directly
8051core-Verilog
- 8051内核的verilog描述，对学习EDA和处理器设计很有用的资料。-The disigning of the core 8051 using verilog language.