搜索资源列表
18_uart
- 通过FPGA建立模块的串行的Verilog实现-Realized through the establishment of the module s serial verilog on FPGA
ethernet_tri_mode
- 以太网通信verilo实现UDP、TCP传输。-ethernet verilog，udp，tcp
clock
- Verilog实现时钟和闹钟功能，可以设置初始时间，调节时间。-Verilog realize the clock and alarm clock function, you can set the initial time, adjust the time.
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
AD9226_acq
- 运用verilog语言实现芯片AD9226的传输-Using verilog language to achieve the transmission of chip AD9226
idwt
- Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse
spi
- 使用verilog语言实现spi传输协议(Using Verilog language to implement SPI transport protocol)
rx_tx_interface_demo
- 精简的verilong串口通信源码，带通信自定义模块(Streamlined verilong serial communication source code, with communication custom module)
常用加法器设计
- 采用Verilog设计的几种常用加法器。(several adder designed by Verilog)
SystemVerilog 3.1a中文+英文版
- Sytem Verilog 语言的设计事项(SystemVerilog user Guide)
RS编译码器verilog
- 本设计提供RS（255，247）码的编码和解码的Verilog源代码。 已验证0~4个错误的编码与解码功能。
计数器
- 简单的硬件描述语言verilog语言描述的128进制计数器。(Simple hardware descr iption Language Verilog language described 128 binary counter.)
shiyan
- 0到59分59秒运动计时器，带有复位开始暂停按键功能(0 to 59 minutes and 59 seconds of motion timer with reset pause button start function)
DACVERILOG
- DAC IC AD9708Driver code,use verilog hdl,Can output sine wave, cosine wave
Verilog-HDL实用教程（张明）
- verilog教程，更加偏向工程化的verilog实用教程，有很多实际模块，推荐(Verilog tutorial, more biased toward the engineering of the Verilog practical tutorial, there are many practical modules, recommended)
A4_Clock_Top1
- 描述了一个数字时钟，同时通过按键调整时间(descr iption of a digital clock, at the same time adjustment of time by keys)
xiaodou
- 利用Verilog语言进行编写的V代码，实现的按键消抖功能(The V code written in Verilog language is used to realize the function of button dithering.)
dac8560 VERILOG驱动程序
- dac8560 VERILOG驱动程序，输出波形，使用时把.txt改成.v
Verilog实例代码
- 一些verilog模块的代码与tb，常见的同步异步FIFO，RAM和适合新手学习
fir滤波器
- FIR滤波器，verilog编写，可以正常使用(FIR filter, written by verilog, can be used normally, very good)