搜索资源列表
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version
my_232
- verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Quartusrs232
- 串口通讯，与硬件联通调试过，收发程序是分开的。-Serial Communication
FPGA
- 使用VHDL实现的串口通信程序，主要完成利用串口收发数据等功能 -Using the VHDL implementation of the serial communication program, primarily the completion of functions such as send and receive data using serial port
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
rt
- 用Verilog编写的串口收发程序，通过参数调整，就可以设定/更改波特率，收发数据长度，已调试。-Serial transceivers with Verilog program, prepared by adjusting parameters, you can set/change the baud rate, send and receive data length, is debugging.
uart
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于
serial
- 简单串口收发程序，完成串口数据收发，波特率9600bps-A Simple Transceiver Program
uartverilog
- 该程序是Verilog写的串口收发程序，具有基本的收发功能，经过验证，能使初学者很好了解rs232，和Verilog-The program is written in Verilog serial transceiver program, with the basic send and receive functions, proven, good for beginners can understand rs232, and Verilog
EP3C
- 利用Verilog编写的串口收发程序，波特率可调，经测试完全可以应用。-Use of serial transceiver in Verilog program, the baud rate is adjustable, can be applied by the test completely.
UART
- 异步串口收发程序，波特率4800。VHDL写成。在ALTERA开发板上测试成功。-This is a UART program, with a fixed 4800bps. Tested successfully on an Altera divice.
uart_rx_tx
- 基于sp605开发板的一个串口收发程序。包含了所有ise产生的完整的文件（ucf等），通过串口调试助手测试通过。共有四个模块构成。-Program based on the the sp605 development board serial transceiver. Contains all ise complete file (ucf etc.), by serial debugging aides tests. A total of four modules.
uartverilog
- 串口收发程序verilog版本，适用于ALTERA的CPLD-Serial transceiver Verilog version, applicable in ALTERA CPLD
uart16
- verilog hdl语言，16位串口收发程序，波特率96-verilog hdl uart 16 9600
baud_gen
- 运用VHDL语言，实现串口收发程序中的波特率设置的子程序，可以将该子模块加载到主程序中。-VHDL language, set the baud rate of the serial transceiver subroutine, this sub-module is loaded into the main program.
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
uartverilog
- FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)