搜索资源列表
DDS_sine
- DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
zhengxian
- 实现了ASK,PSK,FSK调制信号产生的数字信号源-To achieve the ASK, PSK, FSK modulation signal generated by digital signal source
12864PDDS
- 12864显示DDS信号源，包括protues仿真，还有程序-12864 DDS display source, including protues simulation, as well as program
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
dds
- 采用dds技术实现信号源，可产生正弦载波，载波幅度和频率均可调整。-Dds source technology used, can produce a sinusoidal carrier, the carrier amplitude and frequency can be adjusted.
e_pro_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
gnss_xinhao
- GNSS信号源vhdl代码，时钟为40MHZ，脉宽1us,可为gnss应用提供信号源-Vhdl code of the GNSS signal source clock of 40MHZ, pulse width 1us, can provided for gnss application source
DDS
- DDS信号源项目总结，本文是基于FPGA的DDS设计，采用的是SPCE061A单片机的AD9851模块-DDS signal source project summary，This article is based on the FPGA DDS design, using SPCE061A microcontroller AD9851module
Choosing-signal-generator
- 基于FPGA的模拟信号源设计（中英文翻译） CPLD 信号发生器 频率捷变 无线电-FPGA signal generator frequency-agile
DDS_total
- quartus下的DDS信号源设计，可实现多种波形不同频率和幅度的切换，人机界面友好。-design the quartus under the DDS source, can achieve a variety of waveforms of different frequencies and amplitude switching, friendly interface.
dds_quicklogic-FPGA
- dds_quicklogic FPGA DDS信号源-dds_quicklogic FPGA
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
shudian
- DDS信号源设计，通过频率控制字k可以自动调节波形频率的输出-DDS signal source design, frequency control word k can automatically adjust the frequency of the waveform output
cmi
- 运用4阶m序列产生信号源 即消息码 用verilog编程实现cmi的产生-The use of fourth-order m-sequence generator source message code Verilog programming cmi generation
DDS_SYS_CLK100M
- 基于FPGA的信号源设计，100M时钟，32位相位累加，能产生正玄波、方波，三角波，锯齿波，频率可调，频率范围0.03HZ-15MHZ。-FPGA-based signal source design, 100M clock, 32-bit phase accumulation can produce sine wave, square wave, triangle wave, sawtooth, adjustable frequency, the frequency range 0.03 Hz
VHDL-DDS
- 基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
DDS_dac9764
- verilog语言编写的DDS信号源，采用DAC9764-verilog DDS signal source language, using DAC9764
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
sanjiaobo
- DDS信号源中关于三角波的设计，程序上采用VHDL编写，结果仿真通过-DDS signal source on the triangle wave design, procedural preparation of VHDL simulation results through