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同步复位与异步复位问题
- 同步复位与异步复位问题,应用于EDA设置,适合初学者-asynchronous and synchronous reset reduction, EDA application settings for beginners
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
异步FIFO的VERILOG实现(格雷码)
- 使用格雷码实现异步FIFO
7位二进制计数器
- 应用VHDL语言编写设计一个带计数使能、异步复位、同步装载的可逆七位二进制计数器,计数结果由共阴极七段数码管显示
实验8 含异步清零和同步使能的计数器的设计
- 该压缩包内是一个含异步清零和同步清零的计数器,内还有源代码以及说明文档
用 vhdl 设计含异步清零和同步时钟使能
- 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。 -With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter
Verilog
- 异步fifo的经典写法,使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
FIFO
- 用verilog实现异步FIFO,代码中有两个模块,使用时注意顶层模块和底层模块,用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
altera_fifo
- altera 公司的 FIFO 文档,这是设计同步或异步FIFO的重要文档-altera s FIFO document
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
FIFO
- 异步FIFO的实现,可综合,可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
UART_VHDL
- 异步串口通信VHDL源代码,通过了验证,最高通信速率可达384-Asynchronous serial communication VHDL source code, through the validation, the maximum communication rate of up to 384
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计,供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
uart_verilog
- 用verilog编写的标准异步串行通行程序,供大家参考!-Prepared using Verilog standard asynchronous serial passage procedures for your reference!
75448172geleicounter
- 这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷(GRAY)变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点,使得整个系统可靠性高和抗干扰能力强,系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构,使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
uart
- 基于FPGA的uart源代码,异步串行通信,vhdl书写的。-uart codes。write with vhdl.
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
异步FIFO
- 纯Verilog实现的异步FIFO,分为读写控制模块,SRAM CORE,同步等几个模块,内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)