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JPEG2000_FPGA_Design
- 本论文主要论述JPEG2000中嵌入式块编码的FPGA设计，非常有参考价值-this paper mainly discusses JPEG2000 coding embedded blocks of FPGA design, a very valuable reference
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Stage3_3175133_Zhang
- 用MATLAB里的XILINX BLOCKS, 支持FPGA算法, 实现X_NEXT = ((n-1)x+ A/x(n-1)次)/n
Stage3_Library
- 用MATLAB里的XILINX BLOCKS编写, 做嵌入式用的2个BLOCKS, 一个为除法BLOCK, 另一个为乘方BLOCK.
Fibonacci_sequence
- 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.
ltc1196.rar
- TLC1196串行AD控制模块，可以实现对电压的信号采集，并以串行的方式传送到FPGA中,TLC1196 Serial AD control module can be achieved on the voltage of the signal acquisition, and serial transmission of the FPGA
verilog_intr
- Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks –
UART_SUCCESS
- 实现FPGA和上位机的串口通信，里面由波特率发生器，移位寄存器，计数器，detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function bl
XAPP220
- LFSRs as Functional Blocks in Wireless Applications
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
count100
- 一个用VHDL语言编写的一百进制计数器。软件平台是Quartus II 7.2 ，由前面设计的小模块组合起来制作的，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a binary counter 100. The
DISPLAYS_FINAL
- Program in VHDL. Developed for the spartan 3 kit. It is composed of 4-bit adder, with the result in the display board. It blocks the conversion of binary to BCD and multiplexed displays.
SystemVerilogImplicitPorts
- The Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of
C20_SD
- 主要实现在通过FPGA NIOS中，对SD进行初使化，读，写文件内容，但其是以块的形式写进SD里的，而不是以.TXT形式写入的。-Mainly achieved through the FPGA NIOS, the pairs of SD to perform initialization, reading and writing file content, but it is in the form of blocks written into the SD inside, rather th
OFDM
- this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks-this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks
RAM
- this code is for the ram blocks and it is very essential if you are going to implement asic
11912890arith_lib_cadence
- VHDL中的一些常用功能块，源码，以及一些常用库，好多好多的。-VHDL some of the common functional blocks, source code, as well as some common libraries, many many of the.
gr-my-blocks-template
- design a basic signal processing block. Templates to create new blocks