搜索资源列表
SPI_VHDL
- SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
spi_master
- 基于CPLD/FPGA的SPI控制的IP核的实现spi_master
an485_design_example
- AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序
- vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
slave_spi_ctrl.rar
- SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集,SPI control course code
cpld_spi
- cpld spi ，功能基本上满足普通项目的使用，欢迎使用。-cpld spi, function essentially to meet the general project use, Welcome.
SPI_IIC_design_example
- ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
spi.sim
- vhdl spi cpld simulation
spi.tan
- vhdl spi cpld fpga cofiguration
spi
- 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
lunwen
- spi协议简介及简单的spi接口的描述和基于CoolRunner CPLD 的SPI设计结构-Introduction and simple protocol spi spi interface descr iption of the SPI CoolRunner CPLD-based design structure
an487_CN
- 利用 MAX II CPLD 实现 SPI至I 2S 的接口-used the MAX II CPLD to implement the SPI interface with I2C
SPI_to_I2C
- 本设计允许用户使用CPLD作为SPI和I2C接口的桥接芯片。-This design enables an SPI-interface-equipped host to control data flow to other devices such as an A/D converter, LED controller, audio processor to read temperature sensors, hardware monitors, and diagnostic senso
xapp386
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Mas
xapp348
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunne
SPItoIICcodeForAlteraCPLD
- Altera 官方关于SPI和I2C应用的CPLD实现的例子-About SPI and I2C official Altera s CPLD implementation examples of applications
CPLD-SPI
- CPLD实现SPI接口时序，与SPI接口的外部芯片交互通信-CPLD TEST SPI
spi1
- 使用verilog语言编写的实现cpld EPM570与EEPROM的SPI通信-Using verilog language to achieve cpld EPM570 SPI communication with the EEPROM
SPISlavetoPWMGeneration-Source.ZIP
- SPI convert to PWM for CPLd
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is