搜索资源列表
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
61EDA_D59Xilinx-ISE-9.RAR
- Xilinx ISE 9 深入辅导资料，环境使用方法，英文资料，希望有用。-Xilinx ISE 9 in-depth counseling information, environment using the method, information in English, I hope useful.
fifo
- 一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，产生FIFO为空、满、半满、溢出标志。-A synchronous FIFO, the FIFO depth of 16, each storage unit width of 8, asked to produce the FIFO is empty, full, half full, the overflow flag.
stack
- 设计了一个深度为64，字长为16_bit堆栈，要求有栈空、栈满和栈溢出信号。试以双向移位寄存器结构或存储器结构的电路结构方式设计完成电路，并说明它的特点。-Designed with a depth of 64, the word length is 16_bit stack, stack empty, stack full and stack overflow signal. Trial to the way of bi-directional shift register or memory
sbq
- 示波器的深入了解，可以对示波器的更过功能有所了解-In-depth understanding of the oscilloscope, the oscilloscope over function to understand
verilog-compiler
- 本文包含了几个关于Verilog的编译器的源码实现，适用于深入学习Verilog的读者-This article contains several Verilog compiler source for in-depth study of Verilog reader
ise10.1_Tutorial
- 英文原版ISE软件教程，适合硬件开发工作者使用，内容丰富-ISE In-Depth Tutorial
Timing-and-Clocking
- fpga中关于时序与时钟的深度剖析，解释了很多设计时遇到的问题以及解决方案-fpga in depth analysis of the timing clock, explains a lot of the problems encountered in the design and solutions
AlteraPFPGA_CPLD
- FPGA和CPLD的学习资料，从初级到高级，从基础到深入，对于学习FPGA的初学者很有用处。-FPGA and CPLD learning materials, from beginner to advanced, from basic to in-depth for beginners learning FPGA useful.
vhdl_text3
- 设计一个数据宽度8bit，深度是16的 同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz， 将1－16连续写入FIFO，写满后再将其读出来（读空为止）。 仿真上述逻辑的时序-Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output fla
chap11
- 这是关于ＦＰＧＡ第十一节的实验代码可以参考 特权同学的深入玩转ＦＰＧＡ一书进行学习-This is the book depth Fun FPGA FPGA section XI of experimental code can refer to the privileged students learning
BlockRam
- 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
ltc2614_spi_cosx32768
- 基于xilinx spartan 3e 开发板的正弦波信号发生，通过fpga查找ROM正弦信号表,将数字信号通过spi接口写入开发板上的12位DA芯片ITC2614。通过DA转换产生正弦波。ROM深度为32768，表示一个正弦周期最多可以有32768个点。可以通过修改相位累积值和ROM表来设定输出正弦波的频率。程序本人编写和上板实测。-Sine wave signal occurred on xilinx spartan 3e development board fpga Find ROM si
fft256_512_1024
- 基于基2的并行256，1024深度的FFT源代码verilog-Based on radix-2 FFT parallel 256,1024 depth verilog source code
fft4096_8192
- 基于基2的并行4096，8192深度的FFT源代码verilog-Based on radix-2 FFT parallel 4096,8192 depth verilog source code
ISE_ug695_democode
- ISE 14.3的深层次用户手册英文版UG695，包含实例，可以按照说明动手学习-ISE 14.3 in-depth user manual English UG695, including examples, you can follow the instructions for hands-on learning
VHDL
- VHDL简明教程，对于想要学习VHDL的人是里面的资料相当不错，从初学到深入-Concise Guide to VHDL, VHDL for people who want to learn the inside information is quite good, from the beginner to the depth
verilogHDL
- verilogHDL 精粹讲解，还有很多经典实例，有助于大家更深入地学习verilogHDL。-verilogHDL explain the essence, there are many classic examples to help you more in-depth study verilogHDL.
rtc
- NIOS II下进行RTC实时时钟的开发,比较有难度的知识点： 1. PIO的深度应用； 2. C语言中函数指针的应用； 3. DS1302的驱动编写； 4. C语言中程序的模块化书写方式； -NIOS II development for the next RTC real time clock, have more knowledge of difficulty: . 1 PIO depth application 2 Application
FPGA-teach1
- 这是一种Verilog语言的学习资料的第一部分，能够很深入的帮助学习进步-This is the first part of a Verilog language learning materials, and can be very in-depth help learning progress