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signed four bit multiplier
- a multiplier for four bit binary number
four
- 用VHDL语言完成十秒倒计时电路以及四人抢答加分的系统-VHDL language with the completion of 10 seconds countdown circuit and four extra points to answer in the system
four-bit-mul
- 用加法器乘法树实现四位乘法器。绝对可以实现，大家不妨下来-Achieved with the four adder tree multiplier multiplication
Verilog-versions-of-four-models-show
- fpga驱动vga四种样本 用途广泛 这里有许多常用的实验 基础 -Four samples of fpga driver vga There are many widely used common experimental basis
a-four-emitting-diode
- 用veriHDL语言编辑的一个四位二进制+七个发光二极管-VeriHDL language editor with a four of seven light-emitting diode binary+
Four-multipliers-with-VHDL-
- 用VHDL实现四位乘法器，不直接用乘法实现。该代码思路清晰，希望可以帮助到大家！-Four multipliers with VHDL implementation, not directly with the multiplication implementation. The code is clear thinking, I hope to help to you!
four
- 大学VHDL实验科目报告四位全加器设计报告-University of VHDL test subjects reported four full adder design report
Four-Responder
- (1)设计用于竞赛抢答的四人抢答器； .有多路抢答，抢答台数为4； .具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警； .能显示超前抢答台号并显示犯规警报； (2) 系统复位后进入抢答状态，当有一路抢答按键按下，该路抢答信号将其余各路抢答信号封锁，同时铃声想起，直至该路按键松开，显示牌显示该路抢答台号； -(1) is designed to answer in the four competition Responder . More way to an
Four-binary-adder
- 程序1：4位二进制加法计数器（EDA实验中用到的)-Four binary adder
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
Four-adder-of-subtracter
- 在max+plus II 的环境下设计4位全加器数字电路 使用vhdl语言，进行设计数字电路的RTL级电路 -Four full adder digital circuit design environment, max+ plus II RTL-level circuit, digital circuit design using vhdl language
Four-layer--double-Lift
- 四层双电梯智能系统，模块化设计，包括电梯选择，电梯外部控制，电梯内部控制，楼层显示等模块-Four-story elevator intelligent system, modular design, including the elevator choices, external elevator control, elevator internal control, floor display module
four-decimal-frequency--meter
- 基于VHDL语言设计实现的4位十进制的频率计及其在试验箱上的管脚连接-Based on VHDL language design of the realization of the four decimal frequency meter
Four-FPGA-design-techniques
- FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化-FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface
Four-intelligent-responder-
- 四路智能抢答器的VHDL实现，具有开始和复位功能，同时具有答题倒计时功能-Four intelligent responder VHDL implementation, with start and reset function, simultaneously has the answer countdown function
Four-bit-full-adder
- 四位全加器，是自己编写的，如有错误，请原谅-I have written four full adder, is subject to error, please forgive
four-adder-design
- 可编程逻辑设计-用VHDL语言进行四位加法器的设计-Programmable logic design _ four adder design
Four-Consecutive-Ones-Detector
- its a counter of four ones consecutive
VHDL-design-four-Responder
- 1、熟悉四人抢答器的工作原理。 2、加深对VHDL语言的理解。 3、掌握EDA开发的基本流程。 -A familiar four Responder works. 2, to deepen the understanding of the VHDL language. 3, master EDA development of the basic processes.
The-four-locks-Verilog-based-design
- 基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation