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2下载：
verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
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半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
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4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
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synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga.
64x interpolation.
interp_filter.v
interp_first.v
interp_second.v
interp_third.v
upsample.v
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实现了2级cic滤波器的功能，其中内插32倍，即实现了32倍的2级cic内插滤波器-Realize the level 2 cic filter function, including 32 times interpolation i.e. the 32 times the level 2 cic interpolation filter
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DVBS中可变插值率CIC滤波器设计及其FPGA实现-DVBS variable interpolation rate in the CIC filter design and FPGA implementation
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级联优化的半带插值滤波器，分模块设计-Half-band interpolation filter cascade optimization sub-module design.
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cic 滤波器，vhdl代码 ，内插与抽取-cic filter ，vhdl code about decination and interpolation
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基于fpga的插值CIC滤波器设计,采用verilog编写，24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
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4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
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内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用-Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly
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在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co
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多级插值CIC滤波器，3级、过采样率为2的8位CIC插值滤波器，系统工作时钟的频率是数据速率的2倍
-Multi-stage interpolation CIC filter 3, an oversampling ratio of eight CIC interpolating filter, the operation clock frequency of the system 2 is twice the data rate
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CIC interpolation filter which DOESNT WORK-CIC interpolation filter which DOESNT WORK!!
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抽取:(接收端)
中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。
插值:(发送端)
基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。
注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver)
IF signal 20M (sampling rate is 50M) down-conversion signal M
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调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
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