搜索资源列表
FFR_STS
- 一个智能UART的FPGA代码。能给自动根据协议应答-A smart UART FPGA code. Under the agreement will give automatic answering
RTL
- UART RTL测试程序，用于串口调试，红色飓风E16开发板使用-UART RTL test procedures for serial debugging
rxpart
- uart异步串口收模块，将串口数据进行组合变成8位的字节。波特率可自行调节-uart receive asynchronous serial module, serial data will be combined to become 8 bytes. The baud rate of self-regulation
uart_latest.tar
- 串口（UART）的verilog源代码，可以供设计参考-Serial port (UART) of the Verilog source code, can be used for reference in design
uart_tx
- It is an UART interface that is written by me in VHDL to receive and send datas from/to FPGA.
UART_FIFO
- 用VHDL语言实现内置FIFO的UART，并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
my_uart_top
- UART串口传输，参考别人写的，大家修改下就可以用，欢迎参考。-UART serial communication
UART
- URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
ML605_uart
- 本案例是开发xinlinx ml605 FPGA上使用UART通信的简单例程-This case is the development of the xinlinx ml605 FPGA UART communication using simple routine
uart
- RS232串口调试程序，已经经过试验和调试，很方便，带注释-RS232 serial debugger
Verilog_UART
- the file use verilog HDL to realize uart.it contain recive and transmit.-the files use verilog HDL to realize uart.it contain reciver and transmitor.
you_ran
- 串行UART接收，采用VHDL语言，供参考-Universal Asynchronous Receiver/Transmitter
verilog--uart--fpga
- 基于verilog的串口通信实验指导和源程序-Verilog based serial communication experiment guide and source code
COMPLETE-UART_16
- the project is complete a UART implementation where 16 UART are connect with top module for aerial applications-the project is complete a UART implementation where 16 UART are connect with top module for aerial applications
uart_tx
- uart transmitter module in verilog hdl
uart_rx
- receiver module of uart protocol in verilog hdl
1313721777
- nexys3 FPGA开发板的uart nexys 3 串口测试程序-nexys3 FPGA uart
uart_verilog.tar
- 在FPGA上实验UART的verilog源码,可综合,已测试OK.-The experimental UART on FPGA verilog source
rs232_interface
- 这是一个简单的UART 到 uPC 的接口. 可用于FPGA 和计算机的接口.-This is a small UART to uPC interface. Ideal to use with soft/hard processors in a FPGA project
Nexys3_EDK_GPIO_UART_AXI-14-4
- uart-usb 接口 edk nexys3 德致伦