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any_to_1024x768@60
- 将分辨率大于1024x768任意帧频的视频输入转换为1024x768@60Hz VGA输出-The 1024x768 resolution is greater than at any frame rate video input is converted to 1024x768 @ 60Hz VGA output
VideoDecod
- 本程序是视频图像处理的前期部分，功能是通过FPGA控制SAA7113实现视频解码，讲模拟全电视信号转变为数字视频信号，为后期的图像处理算法做准备。-This program is part of the video image pre-processing functions are realized by FPGA control SAA7113 video decoder, speaking analog composite video signal into a digital video
SGDMA_dispatcher
- SGDMA包含以下特性： l 根据描述符进行中断使能 l 包传输长度限制 l 视频帧缓冲驻留 l 不对齐存储器访问 l 静态和可编程突发处理 l 数据位宽高达1024-bit l 独立的收发描述符缓冲 l 支持64-bit地址 (必须使用 Qsys 12.1或之后的版本) l 4GB缓冲传输 l 可编程跨越（以字为单位） l 可编程添加描述符 l 用户可定制功能（提高逻辑和存储器利用率）-SGDMA includes the following f
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect
Video_mixer
- Video transient with support of Fade, Wipe, Cut and Fade to black.
Keyer
- Video Keyer supporting Luminance key, Self key, Matt key and Split key
Black_frezz_det
- Detestor of Black and Freeze in live video-Detestor of Black and Freeze in live video
08-1_VGA_Display_Test_640480
- 基于quartusII开发环境的VGA视频通信程序，很好的资料，欢迎下载-Based on quartusII development environment of VGA video communication program, very good information, welcome to download
FPGADisplay
- 由ISE开发的FPGA工程文件，显示相关，包括视频接口，用Verilog开发，可以参考学习-ISE developed by the FPGA engineering documents, display related, including video interface, using Verilog development, you can refer to learning
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
HDMI_4AV
- 该源码为基于FPGA的HDMI显示的一拖四的AV视频采集。该模块可方便移植在需要使用HDMI高清显示的场合，并且可将VGA显示一分为四，方便各个窗口显示不同的图像信息-The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition displa
RD1213_Video_Pipeline
- This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video streams DVI and SDI inputs and the
xapp897
- Video streaming example VHDL
sdi_3g_hd_sd_code
- SDI格式视频产生代码，fpga编码，里面有3个文件分别对应3g,hd,sd信号，给不同的时钟就可以直接用了-SDI format video generation code
fpga_ladybug_2.1
- 珍藏多年视频GAME之VHD学习资料，超傎-VIDEO GAME STUDY
xst3_video
- 珍藏多年视频GAME之VHD学习资料5-VIDEO GAME VHDL
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有： （1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序
FIFOonFPGAtoUSB
- 这个一个基于FPGA的FIFO的传输资料，可以用在USB的传输上，里面有视频有源代码，还有估计的设计，相关的文档说明等等。-The transmission of a data FIFO of FPGA-based, can be used on USB transmission, which has a video source code, as well as estimates of design, related documentation, and so on.
sdram_ov7670_vga
- 基于FPGA的CMOS摄像头视频采集传输，lcd显示。-FPGA-based CMOS camera video capture transmission, lcd display.
Cam_Cap
- 基于Lattice ＦＰＧＡ的视频图像采集与ＶＧＡ输出-Video Image Acquisition and VGA Output Based on Lattice FPGA