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videodigitalsignalscontroller
- 用fpga技术实现基本的视频信号处理：主题程序；视频图象数据采集程序；sram的读写控制；测试程序-they simply use the basic technology of video signal processing : theme; Video data acquisition procedures; SRAM literacy control; test procedures
5555
- 微波炉定时器集成电路的设计 1、 控制状态机：工作状态状态转换。 2、 数据装入电路：根据控制信号选择定时时间、测试数据或完成信号的装入。 3、 定时器电路：负责完成烹调过程中的时间递减计数和数据译码供给七段数码显示，同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。 -microwave timer IC design a control state machine : state of the state conversion work. 2, data l
blocking
- 基于verilog语言的数据选择器，包括数据选择器的测试模块 -verilog language based on the data selector, including data selection for the test module
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
latch
- 关于闩锁效应的产生机理、触发条件、防止措施以及器件的闩锁测试的一个资料文件-This is a generation of latch-up mechanism , trigger conditions , measures and devices to prevent latch- test data file.
ADC0832_test.rar
- ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.,ADC0832 is an 8-bit conversion of the ADC chip, t
EPM240_Uart
- 基于Quartus II的Verilog编写的Uart串口测试程序。数据收发机LED灯测试。-Based on the Verilog Quartus II prepared Uart serial port test program. LED lamp test data transceiver.
UART
- 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data,
mma7455-IIC-chengxu-C52
- mma7455IIC测试程序C52 外加1602显示和串口数据发送-mma7455IIC test program to display and C52 plus 1602 serial data transmission
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
EX
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
1_LAB
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
test
- PPM编码的VHDL实现，可实现8位并行输入数据转换为串行的PPM编码-PPM coded VHDL implementation can be realized 8-bit parallel input data into a serial coded PPM
test
- xilinx ise6.3编译环境，verilog控制程序。实现对外部ad转换数据自动采集计算，并发送到DSP最后处理-xilinx ise6.3 build environment, verilog control procedures. To achieve automatic data acquisition external ad converter calculated and sent to final processing DSP
test
- I2C读数据，并显示在LED上。现在编译能通过但是仿真不行。求高手指正！-read iic data and displays with LED
test-des
- Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
TLC5620
- 用FPGA做的8位DAC的驱动，数据通过串口发送，测试精度一般。-Drive the use of FPGA in the 8 bit DAC, via a serial port to send data, test precision.