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Synthesizable_FIFO_verilog
- Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
WFIFO-32fifo20070821
- 具有32字节深度的FIFO的SPI通信站。-With 32-byte deep FIFO, SPI communication station.
4Verilog-FIFO
- FIFO的简单编程，该FIFO的深度为4，宽度为32，其接口类型见文件中的图标及其注释。-This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example,
based-on-Xilinx-PCIe-Core-DMA
- 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。 4， DriverStudio生成的
asynchronous-fifo
- 同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块-Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module
FIFO_test
- EP2S90 与 TMS320C6727 进行32位通信时读写FIFO的程序，测试完美通过-EP2S90 read FIFO is performed with the TMS320C6727 32-bit communications program, a perfect test by
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
fifo_uart_vhdl
- 带FIFO的串口收发模块 功能完善32位的fifo-the uart with fifo
LCD1602
- 由于 1602 是慢速设备，根据我们显示网址 32 个字符的架构，我们在顶层设计了一个FIFO, 在开始工作的时候一次性把要显示的字符传到在LCD1602上显示RedCore网址 FIFO中，在1602控制层代码中再从FIFO读出送 去显示，加FIFO的好处是，高速的TOP层可以不用去等待慢速的1602写时序，把两个层次的模块 独立开来。-Since 1602 is a slow device, according to our display URL to 32 charac
[verilog]dcfifo_256x32
- Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.