搜索资源列表
floating_point_adder
- 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
song
- 歌曲是什么名字我忘了，代码仅提供一个用verilog编写音乐的模板，想编写什么音乐就往里边套用格式就行了。 本程序无法用软件实现仿真音乐效果，当然可以仿真波形输出，真实音乐效果需用开发板仿真才行，所以就不附仿真图了 用quartus2软件打开即可。 -What are the names of songs I forgot, the code with verilog only prepared to provide a template for the music, what mu
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
ptos
- 要求：并行输入1 byte，串行输出，无数据时输出高电平，输出格式1100+8bit+奇偶校验+0011（停止位）串行输入，并行输出，检测是否奇偶校验错误，是否有帧传输错误传输每bit数据占16个clock周期 -Requirements: parallel importation of 1 byte, serial output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial inp
div-8.5
- 文件格式：VHDL语言。是自己根据具体需要编写的，并通过时序仿真完全正确。改程序是可以直接解压，然后通过Quartus II打开，编译和仿真。十分方便，好用！-File Format: VHDL language. According to the specific needs of their own prepared, and timing simulation entirely correct. Procedures can be directly diverted to extract,
FPGA_verilog_code_sample
- FPGA实例代码及详细注释 ，word 格式，对初学者很有价值-FPGA code examples and detailed notes, word format, valuable for beginners
analogue-digi-ana-converter
- design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an ana
vhdl-wenjian
- 这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners
T_uart
- CPLD发送模块的实现代码,设计按键检测模块，并将键值通过构造的UART发送模块发送到串口调试工具中查看。--发送格式：1位起始位+8位数据位+1位停止位=10位-CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugg
camera_link
- 对camera_link接口传输过来的信号进行格式转换，将16bit并行转换成串行输出-Right camera_link interface transfer over the signal format conversion will be converted into serial 16bit parallel output
ourdev_247126
- his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The
DDS_spectrum_analysis
- 基于FPGA实现DDS的设计 基于DDS的频谱分析仪的设计 Word 文档-FPGA based DDS DDS design with Word format
ModelSim
- 这是一份ModelSim全汉语教程，讲解的不错哦，很实用。注：pdf格式。-This is a full Chinese ModelSim tutorial to explain the good Oh, very practical. Note: pdf format.
hdlc_1
- 高级链路控制的HDLC发送，写的还行，需要使用93版本的VHDL格式-Advanced Link Control HDLC to send, write that still need to use the 93 version of the VHDL format
police
- 警卫控制系统，主要 控制 电梯系统 ，通过422通讯格式完成与电梯系统之间的 通讯协议。-Security control system, the main control elevator systems, through to complete the 422 communication format, communication protocol between the elevator system.
E1
- 在国际标准组织开放式系统互联（OSI）参考模型下，以太网是第二层协议。10G以太网使用ＩＥＥＥ（电气与电子工程师学会）802.3以太网介质访问控制协议（ＭＡＣ）、ＩＥＥＥ 802.3以太网帧格式以及ＩＥＥＥ 802.3最小和最大帧尺寸。-In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol.
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
reinformationregardingapplicationfee
- paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the
YCbCr2RGB
- 将图像数据Ycbcr格式转换为rgb格式，方便显示器显示。-Converting the image data Ycbcr format to RGB format , facilitating the monitor display.
ieee-templates
- IEEE FORMAT FOR PROJECTS