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2下载：
verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
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用verilog编写的分辨率提高的源代码 采用双线性插值-Written resolution with the verilog source code to improve the use of bilinear interpolation
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运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。-Verilog language using digital integration method, the X axis and Y axis interpolation operations.
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半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
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本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the inter
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复杂的插值函数，用于颜色空间转换
verilog-The complex interpolation function for color space conversion verilog
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4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
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利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
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synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga.
64x interpolation.
interp_filter.v
interp_first.v
interp_second.v
interp_third.v
upsample.v
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CIC内插 内插系数可变，阶数1~6,Verilog版本-Inserted within the CIC interpolation factor variable, the order of 1 to 6, the Verilog version
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基于fpga的插值CIC滤波器设计,采用verilog编写，24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
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利用verilog HDL逐点比较法实现直线和圆弧插补-Use verilog HDL by-point comparison method to achieve linear and circular interpolation
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在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co
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使用verilog实现拉格朗日插值，很有使用价值，有需要的可以参考一下-Use verilog to achieve Lagrange interpolation, very useful value, there is a need to refer to
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This a project which contains a verilog code for Bresenham algorithm for linear interpolation, the code is tested using isim simulator.
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调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
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