CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程 搜索资源 - logic

搜索资源列表

  1. micro.logic

    1下载:
  2. 16通道逻辑分析仪(xilinx XC3S50AN-4TQ144C +CY7C68013A-56PVXC)pcb图纸 使用altium 08打开-schdoc+pcbdoc
  3. 所属分类:VHDL编程

    • 发布日期:2013-01-10
    • 文件大小:1.07mb
    • 提供者:熊小良
  1. logic

    0下载:
  2. 5位的操作数X和Y输入后暂存在寄存器A和B中,两位的操作控制码control暂存在寄存器C中,按照control码的不同,分布实现下列操作: 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中,然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:1.56kb
    • 提供者:ALEX
  1. Fundamentals.of.Digital.Logic.with.VHDL-source.ZIP

    0下载:
  2. <数字逻辑与VHDL设计>代码 作者:STEPHEN BROWN,ZVONKO VRANESIC 边计年译 -《Fundamentals of Digital Logic with VHDL》 [Brown,Vranesic-2005] code Bian Jinian Translation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-15
    • 文件大小:22.34mb
    • 提供者:bake
  1. vhdl-Algorithm-Hard-wired-logic

    0下载:
  2. 大型数字系统设计中,vhdl中从算法到硬线逻辑实现的教程-Large-scale digital system design, vhdl from hard-wired logic algorithm to realize the Tutorial
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:811.05kb
    • 提供者:王辉
  1. TRL_Design_of_a_asynchronous_bit_serial_data_trans

    0下载:
  2. RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据,执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behavi
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.83kb
    • 提供者:吴德昊
  1. ALU8

    0下载:
  2. ALU算术逻辑单元,8位,含源程序以及仿真后的波形图-ALU arithmetic logic unit 8, including source code, as well as post-simulation waveform
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:29.33kb
    • 提供者:赵剑平
  1. clock

    1下载:
  2. 这是一个数字时钟的数字逻辑电路,整个工程打包上传,时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2014-05-17
    • 文件大小:1017.2kb
    • 提供者:ryan
  1. logic

    0下载:
  2. 多通道扫描AD控制逻辑。Verilog语言编写-AD control logic multi-channel scanning
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:125.27kb
    • 提供者:zhangwei
  1. Design_of_Embedded_Control_Systems

    0下载:
  2. This volume presents new results in the design of embedded control systems, each chapter authored by an expert. The text focuses on current issues with new approaches for the analysis and synthesis of discrete systems and is aimed at programmable log
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.9mb
    • 提供者:zhangyung
  1. aludesign

    0下载:
  2. In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmatic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:838byte
    • 提供者:gopan
  1. logic

    0下载:
  2. Verilog descr iption for cell logic
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:529byte
    • 提供者:nani
  1. Digital.Logic.And.Microprocessor.Design.With.VHDL.

    0下载:
  2. 设计数字电路和CPU的教程,使用VHDL语言。国外牛人写的书,很强大,很详细,英文原版电子书。-Digital.Logic.And.Microprocessor.Design.With.VHDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-17
    • 文件大小:4.77mb
    • 提供者:Craftor
  1. Logic_and_Integer_Programming

    0下载:
  2. Logic and Integer Programming. This book combines two related topics which are usually covered in separate texts,namely logic and integer programming (discrete ptimisation). These two subjects have close connections and each is applicable to the o
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-07
    • 文件大小:1.16mb
    • 提供者:Thanh
  1. Digital_Logic_And_Microprocessor_Design_With_VHDL

    0下载:
  2. Digital Logic And Microprocessor Design With VHDL eBook
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-18
    • 文件大小:4.59mb
    • 提供者:Dji
  1. Programmable-Logic-Controllers

    0下载:
  2. Programmable Logic Controllers
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-07
    • 文件大小:1.87mb
    • 提供者:wjantee
  1. Shannon-expansion-of-Boolean-logic

    0下载:
  2. 香农扩展即布尔逻辑扩展,是卡诺逻辑化简的反向运算。香农扩展相当于逻辑复制,提高频率;而卡诺逻辑化简相当于资源共享,节约面积-Shannon expansion of Boolean logic or extension, is simply the reverse Carnot logical operations. Shannon expansion is equivalent to the logical replication, increased frequency and simpl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:40.68kb
    • 提供者:李拉
  1. DSP-Algorithm-logic

    0下载:
  2. 它是一部很好的学习数字信号处理算法逻辑的书籍,文中先介绍了数字信号处理的算法,之后讲解了用Verilog HDL的学习和算法编写-It is a good learning logic digital signal processing algorithms book, the paper introduces the first digital signal processing algorithms, and then explained the study and use of Veril
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-09
    • 文件大小:2.12mb
    • 提供者:fangchao
  1. digital-logic-laboratory-report

    0下载:
  2. 数字逻辑的课程设计。简单模拟了电梯的各种功能。-Digital logic design courses. Simple simulation of the various features of the elevator.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-24
    • 文件大小:505.59kb
    • 提供者:追远
  1. Digital.Logic.And.Microprocessor.Design.With.VHDL

    0下载:
  2. Design Processors & Logic in VHDL. Theory & Examples.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-17
    • 文件大小:4.62mb
    • 提供者:Norbert
  1. Fundamentals of digital logic with verilog

    2下载:
  2. Fundamentals of Digital Logic with Verilog Design
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-11-14
    • 文件大小:6.71mb
    • 提供者:dohai267
« 12 3 4 5 6 7 8 9 10 ... 40 »
搜珍网 www.dssz.com