搜索资源列表
Electronwatch
- This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
uart_vhdl_xilinx
- xilinx的串口仿真程序-xilinx simulator programme of serial port
uart_vhdl_lattice
- lattice的串口仿真的程序- serial port simulated programme of lattice
cuart
- verilog编写的全功能串口-verilog programme of serial port
标准的串口通讯设计VHDL
- 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
c-slow
- This document helps how to programme a fpga using c-slow retiming
WIRELESS
- This file contains source code for DS-CDMA transciver using VHDL. it is having two source codes one is for Transmitter and another is for reciever programme.
0000000000000
- 这是一个简单的滤波程序，可以完成高频信号的滤除～-This is a filter programme!
spi_fpga
- 这是一个Verilogde SPi接口应用程序，经过仿真。-This is a SPI interface programme.
spi_test
- 这是一个完整的spi_test测试程序，经过仿真。-This is a spi_test programme.
voter
- 这是一个多人投票表决器程序，经过仿真正确。-this is a majority_voter programme.
lvds
- 这是一个LVDS程序源文件，经过仿真正确。-this a LVDS source programme.
PROJECT
- 这是LVDS的测试源文件，经运行后正确。-this is a lvds Programme.
ASK0908272
- 自己写的二进制频移监控程序，包含testbench,供大家参考-this is the AsK programme,including testbench
key
- 键盘应用程序,通过键盘控制数码管显示相应的数值-Keyboard application programme
pgvhdl4
- vhdl code spwm programme
pgvhdl5
- document word programme vhdl
pgvhdl444
- docoment programme spwm wave
pgvhdl333
- programme sinusoidale spwm
div_k
- 此程序实现时钟的1/k分频，输入为一个复位信号rst_n,一个时钟信号clk，一个参数k；输出out为一个占空比为50 的时钟，频率为clk的1/k -this verilog programme divid the clock to 1/k in fluquency.