搜索资源列表
prng
- 采用线性同余法的素数模乘同余发生器产生随机数,采用5级流水线设计-Using a linear congruential method prime modulus multiplicative congruential random number generator, using five pipeline design
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
pseudo8
- 8位伪随机序列发生器设计，可以进行时序仿真和功能仿真-The design of 8 bits Pseudo-Random Binary Sequence,you can do Timing simulation and function simulation
LFSRT
- LFSR it generates a random test sequence, this is the .v cod. It works well and there is the attachment doc . enjoy it !!!!!!!!!! -it generates a random test sequence, this is the .v cod. It works well and there is the attachment doc . enjoy it !!!!
GuessGame
- VHDL猜数游戏，系统生成随机数，操作者输入猜测的数字，系统给出输入数字与生成数字的大小关系，并统计猜测次数。可以下板使用-VHDL guessing game, the system generates a random number to guess the number of operator input, digital input and generating system gives the magnitude relationship between the digital and
m_sequence_fpga
- 采用Verilog语言编写的伪随机序列——m序列，可用作通信系统输入数据源。-Use Verilog language- m sequence pseudo random sequence, and can be used as input data sources in communication system.
ssram_latest.tar
- SSRAM接口,就是同步静态随机存取存储器接口整个工程文件，包括从前端verilog设计到后端仿真的整个工程-SSRAM interface is synchronous static random access memory interface entire project, including the design from the front to the back verilog simulation of the entire project
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
rs_decoder_31_19_6_latest.tar
- 31.19解码器- RS code is the BCH code of multi-systerm, after a long time of development, the theory and technology of RS code has been rather mature that it can rectify burst error and random error at the same time, especially burst error. It is widel
weisuiji
- 实现f(x)=1+x^4+x^9的伪随机序列发生器-Pseudo-random Sequence
frame
- verilog编写的帧同步检测代码及仿真程序。帧信息序列用伪随机码表示，同步码为100110-frame synchronization detection code written in verilog and simulation procedures with frame information using a pseudo-random code sequence, and synchronization code 10011011
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
snaketc
- 贪吃蛇游戏机 用一个 8×8 点阵做为基本显示屏，4 个连续移动的的发光点表示一条蛇，用任意出现的一个亮点表示老鼠，用4 个排成一条线的发光点表示“墙”；用两位拨码开关控制蛇的运动方向，蛇撞“墙”、边或者游戏时间到，则游戏结束；老鼠出现的位置是随机的，每次出现的时间是5 秒钟，如果5 秒钟之内没有被吃掉，它就会在其它地方出现；用数码管显示得分情况和游戏剩余时间，每吃掉一次老鼠就加一分。 -Snake game console with a 88 dot matrix display as
PN15
- 伪随机序列的产生，又称为PN码。本文件产生的为PN15，通式为X15+X14+1。-Generation of pseudo random sequences, also known as the PN code. This file is generated for the PN15, the general expression of X15+X14+1.
async_fifo_prj
- Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code
m_serial
- m序列产生。3个300阶m序列级联，产生近似随机的数数。输出包括串行输出的随机时钟和并行输出的32位的随机数。-m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output
caideng8
- 计能让一排灯（8只）自动改变显示花样的控制系统。可将实验板上的一排发光二极管作为彩灯用。控制器应有两种控制方式： ◆规则变化。变化节拍有0.5秒和0.25秒两种,交替出现,每种节拍可有8种花样,各执行一或二个周期后轮换。 彩灯变化方向有单向移动,双向移动,跳跃移动等。 ◆ 随机变化。变化花样相同，但节拍及花样的转换都随机出现。 -Total make a row of lights (8) to automatically change the display pattern
HWL_PRBS_GEN
- Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. PRBS. Verilog language
ren_gen
- xilinx vhdl code for random number generator and prime number check. it can be used for cryptography