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fpga
- FPGA based implementation of an invisible robust image water marking encoder
TheTenCommandmentsofExcellentDesign
- 本资料介绍了FPGA开发过程中优秀设计的十大戒律，可以帮助你设计出更加强壮的硬件程序，值得一读-This document describes the FPGA development process in the ten commandments excellent design can help you design a more robust hardware program, worth reading
15
- Robust H∞ Control of a Doubly Fed Asynchronous Machine
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
god
- This paper presents a novel robust number theoretic transform called inverse Gray Robust Symmetrical Number System (IGRSNS) and proposes its application for CDMA systems. The transceiver structure for three moduli IGRSNS-CDMA with one redunda
fsm
- 有限状态机的一种实现框架，更健壮，更易于表达。-An implementation framework of finite state machines, more robust and easier to express.
spi_verilog_master_slave_latest.tar
- 该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。 所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The resulting co
Coding Files
- Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
pmodkypd_demo_verilog
- 对PmodKYPD矩阵键盘实现检测 输出给数码管显示(robust PmodKYPD source code output towards digital)