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shuzishizhong
- 此代码是FPGA的数字时钟代码，使用的是verilog语言。-This code is the FPGA' s digital clock code, the use of the verilog language.
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
shuzishizhong
- 本实验实现一个能显示小时，分钟，秒的数字时钟。数字时钟-The experimental realization of a can display hours, minutes, seconds, the digital clock. Digital Clock
shuzishizhong
- 用VHDL实现的数字时钟，源代码以调通，能够直接使用！-VHDL implementation of serial communication with the source code to adjust pass, can be used directly!
shuzishizhong
- 可实现数字时钟功能 用于EDA课程实验 有计时，闹钟，还可自行设置调整时间功能-Digital clock function can be used with EDA time course experiment, alarm clock, can set their own time adjustment function
shuzishizhong
- 数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。-Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.
shuzishizhong
- 多功能数字钟具有如下功能 1．秒／分／时的依次显示并正确计数； 2．定时闹钟：实现整点报时，扬声器发出报时声音； 3．时间设置，即手动调时功能：当认为时钟不准确时，可以分别对分／时进行调整；-The multi-function digital clock has the following features 1. Sec/min/turn and correct count 2. Regular alarm clock: the whole point of time,
shuzishizhong
- 简单的数字时钟，能实现闹钟及其时间的定时，设置，通过两位时、分、秒，显示-A simple digital clock
clock
- 数字时钟 带数码显示 并且有异步清零的效果-shuzishizhong
shuzishizhong
- 这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。-This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.
shuzishizhong
- FPGA代码，数字时钟，可调小时，分钟，秒钟，调节时闪烁-digital clock
shuzishizhong
- 基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能-DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board