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CPU
- 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
cpu-16-vhdl
- 用vhdl语用实现简单的16位cpu功能-Pragmatic use vhdl simple function of 16-bit cpu
verilog_design_a_simple_cpu
- 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
CPU
- verilog实现的一个简单的CPU，大家可下载去瞅瞅啊-verilog to achieve a simple CPU, you can download to Chou Chou ah
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
CPU_data_path_design_is_very_simple
- 居于硬件描述语言的简单CPU设计，能够实现比较简单的数据传送处理功能，虽然功能简单，但只要搞懂了其中原理，对于大的系统就能够有依葫芦画瓢的强大效果。-Living in a simple CPU hardware descr iption language design, to achieve relatively simple data transfer processing functions, although the functionality is simple, but as lon
cpu
- fpga实现了简单的cpu，有三个指令，有加法，减法，移动三条指令-fpga to achieve a simple cpu, there are three directives, there is addition, subtraction, move three orders
cpu
- 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.
cpu
- 组成原理实验~简单cpu的设计~基于EDA环境下的-Composition Theory Experiment Design ~ ~ Simple cpu EDA environment based on
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
cpu
- 一个CPU设计的实验，设计了一个很简单的CPU-Experimental design of a CPU, designed a very simple CPU
cpu
- 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
simple-16b-cpu-vhdl-code
- vhdl source code for simple cpu