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8caideng
- 试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左，然后从左到右逐次点亮，全灭全亮；第二种花样为彩灯两边同时亮一个逐次向中间移动再散开；第三种花样为彩灯两边同时亮两个逐次向中间移动再散开；第四种花样为彩灯两边同时亮三个，然后四亮四灭，四灭四亮，最后一灭一亮。四个花样自动变换，重复以上过程。输入时钟频率为500Hz，灯亮的时间在1—4秒之间，可以自由控制。电路中以“1”代表灯亮，以“0”代表灯灭。-Lantern try to design a contro
caidengkongzi
- 设计一个彩灯控制器，彩灯控制器的第1种花样为彩灯从右到左，然后从左到右逐次点亮，接着全灭全亮；第2种花样为彩灯两边同时亮1个，并逐次向中间移动再散开；第3种花样为彩灯两边同时亮2个逐次向中间移动再散开；第4种花样为彩灯两边同时亮3个，然后4亮4灭，4灭4亮，最后1灭1亮。4种花样自动变换，循环往复。-Controller design of a lantern, lantern controller first one kinds of tricks for the lantern from r
xuliejianceqi
- 检测一个5位的二进制序列“10101”（可重复检测），当连续的5个输入为10101时输出为1，其他情况下输入为0。-Detection of a 5-bit binary sequence " 10101" (repeatable test), when successive five input 10101 when the output is 1, otherwise enter 0.
85
- 逐次逼近的VHDL开平方算法,作者：QQ 64134703 ，电子毕业设计，欢迎咨询 -VHDL open square successive approximation algorithm, the authors: QQ 64134703, e-graduate design, please consult
ads7809
- ADS7809是Burr-Brown公司推出的高精度AD采集芯片。它采用5V单电源供电,内含16位 逐次逼近寄存器,采样精度高,功耗小。 用Verilog实现其配置-ADS7809 is a Burr-Brown Introduces High Precision AD capture chip. It uses a single 5V supply, with 16-bit successive approximation register, sampling and high pre
gap_finder
- Design a sequential machine that finds the size of the largest gap between two successive 1s in a X-bit word. Partition the design into a state machine controller and a datapath. The datapath accepts the X-bit word and produces an output word whose v
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
Successive-binary-adder
- Quartus环境下的逐次进位加法器的编写代码，适合初学数字逻辑设计的学习-Successive binary adder in Quartus
verilog
- 八路彩灯控制系统，彩灯可以实现，从左到右顺次亮，全亮后逆次序渐灭。（2）从中间到两边对称地渐亮，全亮后仍由中间向两边逐次渐灭。（3）8路灯分两半，从左至右顺次渐亮，全亮后则全灭。-Eight lanterns control system, the lantern can be achieved, from left to right sequence bright, full brightness gradually eliminate the inverse order. (2) fade
zcjj
- 该算法使用于AD转换，它是运用EDA技术通过对逐次渐进法进行编程实现的，运算快速，正确率高-The algorithm uses the AD converter, it is the use of EDA technology through programming on a successive approximation method, fast computing, the correct rate
SAR-ADC
- 这是一个用于实现逐次逼近型ADC的控制程序，用状态机实现的，用的VHDL语言。在实际项目中测试过-This is a successive approximation type ADC control program, written using the state machine tested in the actual project
SAR-ADC
- Complete Successive approximation Analog to digital converter along with the source code
project3_1
- 逐次进位加法器，HDl verilog语言编写，能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
e10
- 清华大学电子工程系 帧同步器设计实验报告 起始状态定为失步态，通过帧同步码来判断帧的正确性。判断正确则进入预同步态。然后再连续判断两次帧同步码，正确则进入同步态。如果随后的帧的帧头是错误的，则进入保持态以防误码造成的错误。只有在连续发现三次帧头错误才返回失步态。-Electronic Engineering, Tsinghua University, frame synchronizer design experiments starting status report as loss of
ADC_SA_8bit
- the successive approximation part of the circuit. trial_root is loaded with value 8'b1000_0000 on the rising egde that makes count = 3'b000.