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calcu_synthesis
- 本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output
sum
- 这是一个用VHDL写的简易的CPU的程序，共支持10条指令。使用微指令方式。包括.bit文件。下载到FPGA芯片上成功。注解不小心忘记保存。
sum_cash
- 自动售货机的sum－cash源码， 主要负责自动售货机的计算钱和找零的应用。简单实用
cheng1.rar
- 用VHDL实现十六位移位乘法器 才有移位相加法来实现,Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
multiplyingunit
- 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the l
65filter
- 65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole alg
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
multier
- 利用图元实现层次化设计,编程完成数字序列的乘积求和-The realization of the use of pixel-level design, programming to complete the product sum of the number of sequences
subadd
- 一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。-Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computin
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
half_adder
- 一个半加器，具有进位和位数相加的基本功能，可作为全加器的基本模块-One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module
mul
- 用VHDL语言实现十六位加法器（移位相加法）-VHDL language with Multiplier （Shift sum method）
QinYuchu
- 用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！-Vhdl to do with the computer information on the composition of curriculum design principles to achieve the addition operation, a sum, simulation examples, etc.!
8BITCONDITIONALSUMADDER
- it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell
altera_de2_vhdl
- Tutorial of VHDL with Altera DE2 board: quartus II and DE2 board The target do the BCD sum of input data coded with the switches and display the result on 7 segment display
mamta
- the zip file i have uploaded has some testbenches in vhdl for sqare root,sum,subtract
SPA
- 首先介绍了LDPC码的校验矩阵和其因子表示方法，然后利用二分图对和积解码算法进行了详细的描述，最后给出了信度传播概率译码算法详细步骤，并对关键公式作了证明-This paper,first introduces the check matrix and the factor graph of LDPC,then describes the sum-product algorithm by using the factor graph,and finally presents the deta
verilog134
- fpga module adder4(cout,sum,ina,inb,cin)