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ASCII-to-HEX.ASCII码转十六进制数
- labview程序：ASCII码转十六进制数，非常实用的程序,labview procedures: ASCII code to hexadecimal number, a very useful procedure
parallel_to_serial.rar
- 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
counter_0-to-9999
- 数码管计数，在数码管上计数，从0计到-Digital counting experiment, the digital count on, count from 0 to 9999
vga_core(vhdl).rar
- vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中,vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
rgb2ycrcb.rar
- RGB转为YCBCR格式的verilog源代码，对熟悉verilog编程有帮助,RGB to YCbCr format Verilog source code, to people familiar with Verilog programming help
Quartus_II_7.0.rar
- Quartus II 7.0工程修复大法。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误： Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory,Quartus II 7.0 Dafa repair works. Restoration pr
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
YCbCr2RGB
- verilog 实现的YCbCr到RGB得转换-verilog implementation YCbCr to RGB was converted
testbench
- how to write testbench,use vhdl-how to write testbench, use vhdl
bayer2rgb
- bayer到RGB， 12bit进，24bit出，实验效果很理想，简单易用 -bayer to RGB, 12bit entry, 24bit out of the experimental results is very satisfactory, easy to use
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
bujindianji
- vhdl代码！步进电机定位控制系统VHDL程序与仿真！初学者可以参考参考-VHDL code! Stepper motor positioning control system and simulation of VHDL procedures! Beginners can refer to reference
MyState
- 这份是实验课上的教师和学生用的实例。关于用matlab simulink仿真状态机并生成vhdl代码的详细内容-The experimental class teachers and students to use examples. Matlab simulink simulation on the use of state machine and generates VHDL code details
RGBtoYCbCr
- 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
Bin16_BCD5
- it is a binary16 to BCD converter .it will work on spartan 3 xilini devices.
bin2bcd
- Binary to BCD converter
xapp930
- RGB to Y CB CR conversion source code in VHDL
RS232capture
- This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
USB-to-RS232-adapter-module
- 母板通过FR232R芯片及其外围电路实现USB接口转UART（TTL电平）接口，并提供自定义的双列插针扩展接口；功能子板则分为RS232接口和TTL接口两种，并可根据需要设计RS485/RS422/CAN总线接口。-Motherboard chip by FR232R USB interface and its peripheral circuit switch UART (TTL level) interface, and provide a custom double-row pin exp