搜索资源列表
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
usb11_systemc
- USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
usb2[1].0
- usb源码下载，是基于windows开发平台的，通过FPGA加以仿真验证。可以进行数据的传输-usb download the source code is based on the Windows platform, to be adopted FPGA simulation. Can be the transmission of data
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
c8051
- USB v1.1 RTL and design specification
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
usb_funct[1].tar
- usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
dbg_interface
- USB v1.1 RTL and design specification
1
- 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
FPGACPLD
- FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可
usb-blaster
- quartus多种USB-bletera 自制下载线！
1
- 基于USB接口的激光打标控制器设计，CY7C68013
usb11_latest.tar
- its all about implementation of usb 1.1 core
usb1.1
- USB 1.1的verilog代码，已通过fpga 程序源代码内容-Verilog code for USB 1.1, has passed through the contents of the source code fpga
1
- 基于FPGA的USB接口设计，实现了USB与FPGA的通信-USB interface to FPGA-based design, implementation of the USB communication with the FPGA
Altera-Xilinx-Lattice-USB-blaster
- 潜力逐项研究Altera、Xilinx、Lattice的USB下载线。最终希望做成“开源的Altera、Xilinx、Lattice三合一的USB下载线”。填补国内的空白，以及为电子爱好者提供廉价的开发工具。-3 to 1 Altera、Xilinx、Lattice USB blaster
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
USB
- 基于XILINX+ISE+14.1的usb协议设计-Usb protocol design based on XILINX+ISE+14.1
1
- 基于USB接口的边界扫描测试控制器设计,很实用，值得参考。-jtag tap controller