搜索资源列表
mstr_mem32
- Master MemoryExamples for MT32 v1.0.0 Rtl core
PCI-T32
- PCI.VHD, THE INTERFACE MODULE WITH PCI AGENT CHIP --v1.0: For CY7C9689, First Version working on L01A chip --V2.0: For simplified PCI Agent, Xilinx and AMD chips
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能，源码包括控制AD7606进行AD转换，其次实现FT3数据的传输，包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding
usbtrace[1].v1.1
- usb2.0 trace verilog code very useful
DHT22_v1.1
- 我以前曾发过V1.0版的，这是此版的修正版v1.1,修正了以前版本中的一个错误，即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, whic
USBhpi
- USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0\FPGA代码(Quartus)-USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0 \ FPGA code (Quartus)
WP8-Lund-VTC2004-05-05-2004-V1.0
- vhdl for fft and ofdm
stratix_pci_kit-v1.0
- altera PCI总线接口参考设计源代码。使用PCI编译器中的mt64兆核函数实现PCI总线接口-altera PCI bus interface reference design source code. Using the PCI Compiler mt64 trillion nuclear functions for PCI bus interface
armandas-Plong-v1.0-0-g4ccefeb
- fpga protityping is a very interressant document
upf.v1.0
- Unified Power Format Standard
FPGA-lasted-7-days-Altera-v1.0
- verilog 语言，通向FPGA之路---七天玩转Altera 3本，高人总结，对fpga开发很有帮助！经典，教程，vhdl，笔记。-Verilog language, superior to summarize and fpga development to have the help very much! Classic, tutorials, VHDL, notes.
A7105-Datasheet-v1.1
- 无线A7105说明书 0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify descr iption of state machine and FIFO mode Rename IRQS1/
M058_M0516-Product-Brief-SC-V1.0
- 新塘M058_M0516 Product Brief SC V1.0-M058_M0516 Product Brief SC V1.0
rs_204_188----v1.0
- RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；-RS Coding and Decoding Verilog code， implement RS（204,188)
CJQ-V1.0-fpga
- 实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用-it is good ...
lena
- lena v1.0开发板的源代码，实现了对lena FPGA开发板各个部件的调用，直接在此源码上修改即可实现不同的功能-lena v1.0 development board source code, a call to the various components lena FPGA development board, in this modified source code directly to different functions
aes3_rev1.0
- AES3在altera FPGA上开发的参考案例-AES3 Reference Design v1.0 The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock an incoming AES3/EBU stream and stores the parallel audio data and
eda-class-v1.0
- 计算器功能，可加减乘除，可移位,65525以内运算-, calculator functions, addition, subtraction, multiplication, and division can shift, operation within 65525
simwindfarm-v1.0
- GFH GFH DFHFDHD GHDHFDHHFD DFHFDHDF-GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
verilog uart v1.0
- 基于Verilog语言写的UART模块，非常实用，可以参考，希望共同进步(Based on the Verilog language to write the UART module, very practical, you can refer to, hope to make progress together)