搜索资源列表
LED.VHDL
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
基于fpga的多功能电子钟的设计
- 基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊,FPGA-based multi-functional electronic clock design to use would like to help everyone ah
LPT.rar
- 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据 自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。,The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit config
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
clock
- 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
alarm-clock
- 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
lcd_driver
- 用FPGA控制12864液晶输出时钟信息 很好 可以根据自己的需要更改 -12864 LCD control with FPGA clock output information can be very good according to their need to change the
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
FPGA-clock
- 基于VHDL的时钟设计（de2开发平台），内含源代码，各模块的时序仿真图，结构原理图，以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
clock
- 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
FPGA
- 主要介绍VHDL下，电子时钟、LCD、LED、电子琴，电梯等开发程序。-Introduces the VHDL, the electronic clock, LCD, LED, keyboard, elevator and other development programs.
fpga
- 在MAX+plusII软件平台上，熟练运用VHDL语言，完成数字时钟设计的软件编程、编译、综合、仿真，使用EDA实验箱，实现数字时钟的硬件功能。-In the MAX+ plusII software platform, skilled use of VHDL, digital clock to complete the design of software programming, compilation, synthesis, simulation, the use of EDA exper
exam3
- 对sparten 3E fpga的板子的一个各个功能模块的多功能vhdl程序，包括键盘防抖，数字时钟等-Sparten 3E fpga of the board of a multi-purpose function modules vhdl procedures, including keyboard, image stabilization, digital clock, etc.
clock
- 在FPGA下用VHDL语言设计的数字钟程序-Under the FPGA design using VHDL, digital clock program
vhdl
- 用vhdl语言实现的电子时钟加闹铃，程序结构紧凑，由于FPGA的时钟很快，所以时钟非常准确-Electronic clock and alarm, vhdl language program structure is compact, very quickly due to the FPGA clock, the clock is very accurate
clock
- FPGA时钟，vhdl，带设置时间，暂停，开始-FPGA clock
数字钟(8)
- 数字钟（总）整点报时，8位数码管显示。VHDL语言设计。。。。(Digital clock (total) the whole point timekeeping, 8 digital display. VHDL language design....)