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Crack_QII60_b178
- Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
Crack_QII71_b156
- Quartus v7.1的key_gen b156破解器
ASK1
- ASK调制程序 基于VHDL，应用于QUARTUS ,不妨下载
lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
chap3
- adder4 hdl ok in Quartus II 5.1
deccount2.5
- altera Quartus II 減法器使用 配合LED，可自動與手動按鈕控製。 (含電路)
MIF_create
- MIF文件生成器 用于quartus II等软件的ROM表mif文件生成
Quartus+II+++ModelSim+SE+++后仿真+++库文件.rar
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。
Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
seg7_lut_8_0.rar
- 七段阴极数码管的FPGA控制程序，开发平台为ISE或者quartus,Seven-Segment LED cathode the FPGA control procedures, development platform for the ISE or Quartus
flash02
- 一个我自己写的FPGA读写FLASH代码，在QUARTUS 下用verilog编写，falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
1234
- 多功能数字钟，、在quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
ADCCONVER
- 控制CPLD对AD7656进行采样，环境quartus-use the CPLD to control AD7656
sync_vhdl
- 产生复合同步信号波形，可适用QUARTUS来运行并查看波形-Generate composite sync signal waveform, the applicable Quartus to run and view the waveform
cunchuqi
- maxplus环境下通过硬件实现存储器工作的原理展示-maxplus environment through the hardware implementation of the principle of working memory display
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
200681556499797
- 曼彻斯特编解码 用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested
FPGA实验指导书
- 很多程序实例，vhdl语言及quartus平台应用的实用实验资料(A lot of program examples, VHDL language and quartus platform application of practical experimental data)