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i2c.tar
- i2c总线控制器ipcore，包含testbench
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
ethernet_tri_mode_latest[1].tar
- ethernet_tri_mode from opencores.org inlcude rtl and testbench
uart
- verilog实现UART收发源码 内有testbench-the UART transceiver Source for verilog implementation With testbench
7-to-3
- 写出七到三化简表达式并用verilog实现，与传统全加做比较。（内含testbench）-Write seven to three simplification expression verilog achieve, compared with the traditional full. (Including testbench)
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
get_e_de
- 模糊控制器 误差生成模块.V文件及testbench文件-Fuzzy controller error generation module .V file and testbench files