搜索资源列表
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
基于FPGA的巴克码发生器与识别器的设计
- 详细介绍了7位巴克码以及帧同步，7位巴克码与帧同步的关系。-Details of the seven Barker code and frame synchronization, 7 Barker code and frame synchronization relationship.
verilog
- 这是一款学习板的基础实验代码，对于FPGA学习有很好的指导作用。-This is a learning board is based on experimental code, good for the FPGA learning guide。
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
FPGA---buld-gennerate
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
FPGA_uart
- verilog 编写的FPGA串口通信的代码，可实现串口的收发操作-FPGA serial communication code written in verilog serial transceiver operation
FPGA_lcd12864
- 基于FPGA的12864驱动代码，为verilog语言。-FPGA-based 12864 driver code, verilog language.
FPGA-Prototyping-By-Verilog-Examples
- 本书介绍了大量的经典的FPGA开发实例，并附有源代码，是一本很难得外文书籍。-This book presents a classic instance of the FPGA development, together with the source code, it is difficult to get a foreign language books.
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
AD7689_Avalon_core
- ad7869 FPGA驱动程序 采用verilog 编写-ad7869 FPGA verilog code
FPGA-Prototyping-By-Verilog-Examples.pdf
- Book that explains the proper use of verily code and the basics of writing. Examples are also provided
FPGA-RS232
- FPGA与RS232通讯的代码及资料。内含有：RS232发送代码Verilog；RS232接收代码Verilog；RS232协议详细接收WORD文档，也有仿真图哦-FPGA code and RS232 communications and information. Inside contains: RS232 send code Verilog RS232 receive code Verilog RS232 protocol detailed receive WORD document,
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
verilog-2-1-4
- 卷积码（2,1,4）编解码的FPGA实现-Convolution code (2,1,4) decoding the FPGA implementation
coding-style
- 华为FPGA Verilog代码风格，代码规范，适合新手入门-Huawei FPGA Verilog coding style, standardized code, suitable for beginners
ss_drive
- keyboard verilog code for nexys2 fpga borad