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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
EasyClockDivider
- 关于用触发器构建简单分频器的介绍文档，图文并茂，讲解详细-Construction on the simple flip-flop with the divider on file with illustrations to explain the details
FPGA.CPLD
- fpga cpld 常见模块设计，包括基于fpga 的全数字锁向环，基于fpga cpld 的半整数分频器的设计等，很有用-fpga cpld common module design, including fpga-based all-digital locks to the ring, Based on the semi-fpga cpld integer divider design and useful
fenpinqi
- 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
PREDICTION.FRACTIONALN.SPURS
- Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete \"beat-note spurious levels from arbitrary modulus di
pll_component_design_matlab
- PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code
divider
- 中科大微波电路实验，ADS软件设计功分器的方法：包括原理图绘制，电路参数的优化、仿真，版图的仿真等-USTC microwave circuit experiment, ADS software design splitter approach: including schematic drawing, circuit parameter optimization, simulation, layout of the simulation
dividerfrequency
- 分频器，包括2分频，4分频，8分频，16分频；6分频；20分频-Divider, including two-way, 4-way, 8-way, 16 sub-frequency six-way 20 Crossover
15
- 半整数分频器的设计 请不要上传有版权争议的内容和木马病毒代码 -Half-integer divider design, please do not upload copyrighted content and controversial Trojan code
clk4
- clk4 时钟分频设计用于FPGA入门设计-clk4 clock divider is designed for FPGA design entry
shuzipinluji
- 数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement i
jiaotongxinhaodengkongzhiqidesheji
- 本论文主要介绍了红、绿、黄三色交通信号灯较简单的数字逻辑控制电路设计及其原理。本设计方案由定时器、分频器、扭环形计数器、十进制减法器及七段显示译码器实现交通灯红、黄、绿三色的自动切换，在切换灯光颜色的同时进行时间定时状态的切换，使整个交通灯系统得以按照事先设定的定时时间顺利运转。-This paper focuses on the red, green, yellow three-color traffic signal control of the relatively simple digi
si4133-datasheet
- 该Si4133是一个单片集成电路，既执行IF和双频 RF合成为无线通信应用。在Si4133 包括三个和VCO，环路滤波器，参考和VCO分频器，相位 探测器。除法和可编程掉电设置与threewire 串行接口。-The Si4133 is a monolithic integrated circuit, both the implementation of the IF and dual-band RF synthesis for wireless comm
divider
- divider code .. in VHDL language
Combinational_Divider_in_FPGA
- Three VHDL codes for combinational divider with implementation results for Xilinx Spartan FPGAs-Three VHDL codes for combinational divider with implementation results for Xilinx Spartan FPGAs
DividerInt
- VHDL source code for combinational divider with integer types
A-Universal-Programmable-Dual-Divider
- 一种通用的可编程双模分频器A Universal Programmable Dual Divider-A Universal Programmable Dual Divider
Sequential-Divider
- Partial design of a sequential divider using GATES
Fixpoint-Divider
- 定点除法器的设计,关于定点除法器的原理，和设计，以及电路设计-Fixpoint Divider Design
signal-phase-voltage-divider
- 电力系统仿真软件测试（PSCAD、EMTDC），希望对初学者有用-signal phase voltage divider