搜索资源列表
diff_io_top
- LVDS的应用的Verilog HDL例子程序，由altera公司提供。
xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
alteralvds.rar
- 基于altera系列芯片lvds接口的fpga设计 verilog源码,Series altera-based chip interface lvds source fpga design verilog
xapp860
- 16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
hdl
- 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
lvds
- 文章介绍了lvds技术在硬件设计中的原理和应用，先已被广泛应用-This paper introduces lvds in hardware design and application of the principle, first has been widely used
LIP1401CORE_IO_LVDS
- IO LVDS VHDL & Verilog code
7_1LVDS_serilizer
- 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency a
LVDS-application-Verilog-HDL-code
- LVDS的应用的Verilog HDL例子程序-LVDS example of the application procedures for the Verilog HDL
LKB001-U1-LK650-06
- 16通道高速DI数据采集模块程序，采用verilog 编写，quartus，cyclone EP1C3T1-high LVDS comm DI module hollysys bei jing quartus verilog
MATLABtoISEtoCOE
- 艾法斯产品lvds口信号输出下变频程序，网上这方面的资料比较少，verilog主程序-Aeroflex products lvds output port signal downconversion process this information online is relatively small, verilog main
test_3035C
- 成功接收艾法斯产品lvds信号的verilog程序，网上介绍比较少，希望有所帮助-Aeroflex products successfully received lvds signal verilog program, online presentation is relatively small, I hope to help
vhdl
- verilog for LVDS altera stratix4
LVDS_SRC
- 实现LDVS接口数据接收 含有协议结构以及处理-lvds Verilog 512 frame
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
LVDS_to_AXIS
- 8路串行lvds转单路并行axistream(8 single-pathLVDS to 1parallel AXI_Stream)
Altera-LVDS_IP
- 自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, ver
lvds
- XILINX 官方的LVDS IP核，亲测可用。。。。。(XILINX official LVDS IP kernel, pro test available.....)
Lvds_Receiver
- 基于FPGA实现1080p的LVDS 7:1接收程序(Implementation of 1080p LVDS 7:1 receiving program based on FPGA)
LVDS
- 实现了LVDS的发送和接收，本例程增加了握手信号实现，没有用serdes(The sending and receiving of LVDS are realized)