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linux-fifo
- 在linux下使用C语言开发的进程控制程序-the use of C language development process control procedures
用verilog写的对ad0809的控制
- 用verilog写的对ad0809的控制，完整工程，希望对大家能有帮助,Written using Verilog for ad0809 control, complete works, in the hope that we can help
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
Uart(FIFOSend.TimeoutReceive)
- AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
VHDL
- 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
364652261
- FIFO一个用IP核调用的控制程序，里面有调用的IP核和FIFO读写控制-FIFO with an IP core call control procedures, which are called IP core and FIFO read and write control
FIFO
- 该FIFO应当提供用户读使能和写使能输入控制信号，并输出指示FIFO状态的非空和非满信号，FIFO的输入、输出数据使各自的数据总线：in_data和out_data。-The FIFO should be provided to enable users to read and write enable input control signal, and outputs instructions FIFO status signals of non-empty and non-full, FIF
control.h.tar
- this function is about FIFO in page management
FIFO
- FIFO control in the FPGA-FIFO control in the FPGA
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
fifo
- 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
FIFO
- 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
fifo
- FIFO is an acronym for First In, First Out, an abstraction related to ways of organizing and manipulation of data relative to time and prioritization. This expression describes the principle of a queue processing technique or servicing conflicting de
OV7670-FIFO-3.0TFT)
- 控制0v7670，刷出屏幕来，配合tft彩屏，调试通过-The control 0v7670, brush off the screen
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)