搜索资源列表
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
juanjiqi
- 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
conv3
- Program to implement convolution through VHDL-Program to implement convolution through VHDL...
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
k_9_rate_1-2_VHDL
- viterbi generator its very good for convolution
convolution_calculator_4_bits
- convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
juanji
- 采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用-Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
convolution
- convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
convol_enc
- VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.
conv3
- It is a vhdl file for convolution-It is a vhdl file for convolution......
prepha_conj
- 本代码用VHDL实现了复数的卷积，也许对你会有用-this code written by VHDL completes the convolution of complex numbers,which may be quite helpful to you.
viterbi_1
- low power convolution encoder and Viterbi decoder using vhdl code
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
基于VHDL卷积交织器的设计与实现
- 基于VHDL卷积交织器的设计与实现(1)(Design and implementation of convolution Interleaver Based on VHDL)