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数字系统设计教程4_9
- vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar
- FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
计算机设计与实践实验 16位cpu设计
- 计算机设计与实践实验 16位cpu设计 使用用VHDL语言 -16-bit cpu design with VHDL
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
cpu
- 计算机组成原理假期课程设计“一个简单的CPU设计”，有全部的设计思路，能够实现四条简单指令-Principles of Computer Organization holidays curriculum design
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
CPU
- CPU 设计，不错的哦，顶一下哈，希望大家都弄成免费的-CPU design, good Oh, the top click Kazakhstan, I hope we all have to face free
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
cpu
- 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
RISC_SPM
- 简单risc cpu设计，本人通过书中的代码，又加了一些，已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
16位CPU设计
- 给定指令系统的处理器设计，VHDL语言，包括代码和仿真波形
mul_cycle_cpu_1
- 多周期CPU设计详细代码及在ISE下面的仿真(Multi cycle CPU design detailed code and simulation)
实验7.2——多级流水CPU设计
- 当时的课程设计，16位多级无cache流水cpu的源码(Curriculum design at that time, 16 multi-level non cache flow CPU source code)
CPU
- 基于Basys3的16位CPU设计，含有指令集，可以控制Basys3的LED灯，并且通过板子上的开关，调节流水灯的模式(16 bit CPU design based on Basys3, containing instruction set, can control the Basys3 LED lights, and through the switch on the board, adjust the water lamp mode)
CPU
- 基于ARM指令集自主进行CPU设计体验，第一版(Independent CPU design experience based on ARM instruction set, first edition)