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标准SDR SDRAM控制器参考设计_verilog_lattice
- 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
sdr sdram controller
- ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
very-good-ok-ref-ddr-sdram-verilog
- Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
ref-sdr-sdram-verilog
- sdram的控制器 verilog源码
ref-sdr-sdram-verilog
- sdram控制器的开发程序，还有文档，可以参考以下
verilog 128位 突发4. sdr fpga控制器
- verilog 128位 突发4. sdr fpga控制器,verilog 128 bit unexpected 4. sdr fpga controller
(fpga)sdram.rar
- verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
HY57V641620HG.vp.rar
- Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现,Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
SDRAM-control
- SDRAM控制器的Verilog源代码，主要用于SDR-SDRAM-SDRAM controller
sdram-control-verilog
- SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
SDRAMController
- xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
ref-sdr-sdram-verilog
- SDRAM控制器，使用verilog编写-SDRAM controller, use the write verilog
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计，希望有所帮助-sdram and verilog implent
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
83399055ref-sdr-sdram-verilog
- Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences,
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA