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verilog数字时钟论文及代码
- verilog数字时钟论文及源代码
digitalclock
- Verilog数字时钟 实现24小时的监控,用七段码显示出来,包含时序图等 在ISE下仿真-digital clock Verilog
clock
- 本实验实现一个能显示小时,分钟,秒的数字时钟(贝一特电子)Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
verilog
- 多功能数字时钟的verilog语言描述,基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
verilog
- verilog语言编写的数字时钟程序,有计时,校准等功能-verilog language digital clock program
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发,实现了计时,日期,跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
FPGA-verilog-digital-clock
- FPGAverilog数字时钟,基于quartal ii 下的数字时钟电路程序-FPGA verilog digital clock
Electric_clock
- Verilog数字时钟,已实现Diamond环境仿真与FPGA硬件测试-Verilog digital clock, has achieved Diamond FPGA hardware simulation and test environment
8位数字显示的简易频率计
- (1)能够测试10HZ~10MHZ的方波信号; (2)电路输入的基准时钟为1HZ,要求测量值以8421BCD码形式输出; (3)系统有复位键; (4)采用分层次分模块的方法,用Verilog HDL进行设计,并对各个模块写出测试代码; (5)具体参照说明文档(包含源代码,仿真图,测试波形,详细的设计说明)(A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the ci
kcsj
- 利用Verilog层次化设计的多功能数字时钟,可以调时,设置闹钟,仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
Digital_Clock
- 用verilog写的数字时钟代码,亲测可用,可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
至简设计法--闹钟
- 闹钟 工程说明 本工程包括矩阵键盘和数码管显示模块,共同实现一个带有闹钟功能、可设置时间的数字时钟。 案例补充说明 我们通过建立四个清晰直观的模块(数码管显示模块,矩阵键盘扫描模块,时钟计数模块,闹钟设定模块),以及建立完善的信号列表和运用verilog语言编写简洁流畅的代码,实现电子闹钟时、分、秒计时以及设置、修改、重置等功能。(alarm clock Engineering descr iption This project includes matrix keyboard and di
A4_Clock_Top
- 24小时制数字时钟,可自行调节时间,能暂停。(24 hours digital clock, can adjust time, can pause.)
shiyan
- 用verilog语言实现数字中, 在fpga上实现(Using Verilog language to achieve digital, implemented on FPGA)
clock
- 数字时钟的实现,数码管显示,实现时分秒的显示(The realization of the digital clock)
clock_shiyan
- 数电课程设计,数字时钟,基于Quartus II设计(Digital electric course design, digital clock)
digitial_clk
- 使用Verilog写时分秒数字时钟,实现基本的时钟计时功能。(Use Verilog to write time-division-second digital clocks for basic clocking.)
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
A4_Clock_Top1
- 描述了一个数字时钟,同时通过按键调整时间(descr iption of a digital clock, at the same time adjustment of time by keys)